func_cntl         989 drivers/gpu/drm/radeon/rs780_dpm.c 	u32 func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
func_cntl         990 drivers/gpu/drm/radeon/rs780_dpm.c 	u32 ref_div = ((func_cntl & SPLL_REF_DIV_MASK) >> SPLL_REF_DIV_SHIFT) + 1;
func_cntl         991 drivers/gpu/drm/radeon/rs780_dpm.c 	u32 post_div = ((func_cntl & SPLL_SW_HILEN_MASK) >> SPLL_SW_HILEN_SHIFT) + 1 +
func_cntl         992 drivers/gpu/drm/radeon/rs780_dpm.c 		((func_cntl & SPLL_SW_LOLEN_MASK) >> SPLL_SW_LOLEN_SHIFT) + 1;
func_cntl        1011 drivers/gpu/drm/radeon/rs780_dpm.c 	u32 func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
func_cntl        1012 drivers/gpu/drm/radeon/rs780_dpm.c 	u32 ref_div = ((func_cntl & SPLL_REF_DIV_MASK) >> SPLL_REF_DIV_SHIFT) + 1;
func_cntl        1013 drivers/gpu/drm/radeon/rs780_dpm.c 	u32 post_div = ((func_cntl & SPLL_SW_HILEN_MASK) >> SPLL_SW_HILEN_SHIFT) + 1 +
func_cntl        1014 drivers/gpu/drm/radeon/rs780_dpm.c 		((func_cntl & SPLL_SW_LOLEN_MASK) >> SPLL_SW_LOLEN_SHIFT) + 1;