GSL_SOURCE_SELECT   89 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SR(GSL_SOURCE_SELECT),\
GSL_SOURCE_SELECT  167 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	uint32_t GSL_SOURCE_SELECT;
GSL_SOURCE_SELECT  294 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SF(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, mask_sh),\
GSL_SOURCE_SELECT  295 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SF(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, mask_sh),\
GSL_SOURCE_SELECT  296 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	SF(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, mask_sh),\
GSL_SOURCE_SELECT  157 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c 		REG_UPDATE(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, gsl_ready_signal);
GSL_SOURCE_SELECT  160 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c 		REG_UPDATE(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, gsl_ready_signal);
GSL_SOURCE_SELECT  163 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c 		REG_UPDATE(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, gsl_ready_signal);