fsl_dev            27 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c 	struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
fsl_dev            30 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c 	regmap_write(fsl_dev->regmap,
fsl_dev            49 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c 	struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
fsl_dev            56 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c 	regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE,
fsl_dev            59 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c 	regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
fsl_dev            61 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c 	clk_disable_unprepare(fsl_dev->pix_clk);
fsl_dev            68 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c 	struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
fsl_dev            70 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c 	clk_prepare_enable(fsl_dev->pix_clk);
fsl_dev            71 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c 	regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE,
fsl_dev            74 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c 	regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
fsl_dev            83 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c 	struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
fsl_dev            84 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c 	struct drm_connector *con = &fsl_dev->connector.base;
fsl_dev            89 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c 	clk_set_rate(fsl_dev->pix_clk, mode->clock * 1000);
fsl_dev           103 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c 	regmap_write(fsl_dev->regmap, DCU_HSYN_PARA,
fsl_dev           107 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c 	regmap_write(fsl_dev->regmap, DCU_VSYN_PARA,
fsl_dev           111 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c 	regmap_write(fsl_dev->regmap, DCU_DISP_SIZE,
fsl_dev           114 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c 	regmap_write(fsl_dev->regmap, DCU_SYN_POL, pol);
fsl_dev           115 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c 	regmap_write(fsl_dev->regmap, DCU_BGND, DCU_BGND_R(0) |
fsl_dev           117 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c 	regmap_write(fsl_dev->regmap, DCU_DCU_MODE,
fsl_dev           119 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c 	regmap_write(fsl_dev->regmap, DCU_THRESHOLD,
fsl_dev           136 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c 	struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
fsl_dev           139 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c 	regmap_read(fsl_dev->regmap, DCU_INT_MASK, &value);
fsl_dev           141 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c 	regmap_write(fsl_dev->regmap, DCU_INT_MASK, value);
fsl_dev           149 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c 	struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
fsl_dev           152 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c 	regmap_read(fsl_dev->regmap, DCU_INT_MASK, &value);
fsl_dev           154 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c 	regmap_write(fsl_dev->regmap, DCU_INT_MASK, value);
fsl_dev           168 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c int fsl_dcu_drm_crtc_create(struct fsl_dcu_drm_device *fsl_dev)
fsl_dev           171 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c 	struct drm_crtc *crtc = &fsl_dev->crtc;
fsl_dev           174 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c 	fsl_dcu_drm_init_planes(fsl_dev->drm);
fsl_dev           176 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c 	primary = fsl_dcu_drm_primary_create_plane(fsl_dev->drm);
fsl_dev           180 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c 	ret = drm_crtc_init_with_planes(fsl_dev->drm, crtc, primary, NULL,
fsl_dev            13 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.h int fsl_dcu_drm_crtc_create(struct fsl_dcu_drm_device *fsl_dev);
fsl_dev            56 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c 	struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
fsl_dev            58 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c 	regmap_write(fsl_dev->regmap, DCU_INT_STATUS, ~0);
fsl_dev            59 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c 	regmap_write(fsl_dev->regmap, DCU_INT_MASK, ~0);
fsl_dev            64 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c 	struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
fsl_dev            67 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c 	ret = fsl_dcu_drm_modeset_init(fsl_dev);
fsl_dev            79 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c 	ret = drm_irq_install(dev, fsl_dev->irq);
fsl_dev           117 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c 	struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
fsl_dev           121 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c 	ret = regmap_read(fsl_dev->regmap, DCU_INT_STATUS, &int_status);
fsl_dev           130 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c 	regmap_write(fsl_dev->regmap, DCU_INT_STATUS, int_status);
fsl_dev           165 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c 	struct fsl_dcu_drm_device *fsl_dev = dev_get_drvdata(dev);
fsl_dev           168 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c 	if (!fsl_dev)
fsl_dev           171 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c 	disable_irq(fsl_dev->irq);
fsl_dev           173 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c 	ret = drm_mode_config_helper_suspend(fsl_dev->drm);
fsl_dev           175 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c 		enable_irq(fsl_dev->irq);
fsl_dev           179 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c 	clk_disable_unprepare(fsl_dev->clk);
fsl_dev           186 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c 	struct fsl_dcu_drm_device *fsl_dev = dev_get_drvdata(dev);
fsl_dev           189 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c 	if (!fsl_dev)
fsl_dev           192 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c 	ret = clk_prepare_enable(fsl_dev->clk);
fsl_dev           198 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c 	if (fsl_dev->tcon)
fsl_dev           199 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c 		fsl_tcon_bypass_enable(fsl_dev->tcon);
fsl_dev           200 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c 	fsl_dcu_drm_init_planes(fsl_dev->drm);
fsl_dev           201 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c 	enable_irq(fsl_dev->irq);
fsl_dev           203 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c 	drm_mode_config_helper_resume(fsl_dev->drm);
fsl_dev           241 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c 	struct fsl_dcu_drm_device *fsl_dev;
fsl_dev           254 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c 	fsl_dev = devm_kzalloc(dev, sizeof(*fsl_dev), GFP_KERNEL);
fsl_dev           255 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c 	if (!fsl_dev)
fsl_dev           261 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c 	fsl_dev->soc = id->data;
fsl_dev           270 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c 	fsl_dev->irq = platform_get_irq(pdev, 0);
fsl_dev           271 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c 	if (fsl_dev->irq < 0) {
fsl_dev           273 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c 		return fsl_dev->irq;
fsl_dev           276 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c 	fsl_dev->regmap = devm_regmap_init_mmio(dev, base,
fsl_dev           278 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c 	if (IS_ERR(fsl_dev->regmap)) {
fsl_dev           280 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c 		return PTR_ERR(fsl_dev->regmap);
fsl_dev           283 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c 	fsl_dev->clk = devm_clk_get(dev, "dcu");
fsl_dev           284 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c 	if (IS_ERR(fsl_dev->clk)) {
fsl_dev           286 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c 		return PTR_ERR(fsl_dev->clk);
fsl_dev           288 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c 	ret = clk_prepare_enable(fsl_dev->clk);
fsl_dev           297 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c 		pix_clk_in = fsl_dev->clk;
fsl_dev           305 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c 	fsl_dev->pix_clk = clk_register_divider(dev, pix_clk_name,
fsl_dev           308 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c 	if (IS_ERR(fsl_dev->pix_clk)) {
fsl_dev           310 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c 		ret = PTR_ERR(fsl_dev->pix_clk);
fsl_dev           314 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c 	fsl_dev->tcon = fsl_tcon_init(dev);
fsl_dev           322 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c 	fsl_dev->dev = dev;
fsl_dev           323 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c 	fsl_dev->drm = drm;
fsl_dev           324 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c 	fsl_dev->np = dev->of_node;
fsl_dev           325 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c 	drm->dev_private = fsl_dev;
fsl_dev           326 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c 	dev_set_drvdata(dev, fsl_dev);
fsl_dev           339 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c 	clk_unregister(fsl_dev->pix_clk);
fsl_dev           341 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c 	clk_disable_unprepare(fsl_dev->clk);
fsl_dev           347 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c 	struct fsl_dcu_drm_device *fsl_dev = platform_get_drvdata(pdev);
fsl_dev           349 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c 	drm_dev_unregister(fsl_dev->drm);
fsl_dev           350 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c 	drm_dev_put(fsl_dev->drm);
fsl_dev           351 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c 	clk_disable_unprepare(fsl_dev->clk);
fsl_dev           352 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c 	clk_unregister(fsl_dev->pix_clk);
fsl_dev           196 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h int fsl_dcu_drm_modeset_init(struct fsl_dcu_drm_device *fsl_dev);
fsl_dev            22 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_kms.c int fsl_dcu_drm_modeset_init(struct fsl_dcu_drm_device *fsl_dev)
fsl_dev            26 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_kms.c 	drm_mode_config_init(fsl_dev->drm);
fsl_dev            28 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_kms.c 	fsl_dev->drm->mode_config.min_width = 0;
fsl_dev            29 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_kms.c 	fsl_dev->drm->mode_config.min_height = 0;
fsl_dev            30 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_kms.c 	fsl_dev->drm->mode_config.max_width = 2031;
fsl_dev            31 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_kms.c 	fsl_dev->drm->mode_config.max_height = 2047;
fsl_dev            32 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_kms.c 	fsl_dev->drm->mode_config.funcs = &fsl_dcu_drm_mode_config_funcs;
fsl_dev            34 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_kms.c 	ret = fsl_dcu_drm_crtc_create(fsl_dev);
fsl_dev            38 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_kms.c 	ret = fsl_dcu_drm_encoder_create(fsl_dev, &fsl_dev->crtc);
fsl_dev            42 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_kms.c 	ret = fsl_dcu_create_outputs(fsl_dev);
fsl_dev            46 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_kms.c 	drm_mode_config_reset(fsl_dev->drm);
fsl_dev            47 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_kms.c 	drm_kms_helper_poll_init(fsl_dev->drm);
fsl_dev            52 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_kms.c 	drm_mode_config_cleanup(fsl_dev->drm);
fsl_dev            24 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_output.h int fsl_dcu_drm_encoder_create(struct fsl_dcu_drm_device *fsl_dev,
fsl_dev            26 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_output.h int fsl_dcu_create_outputs(struct fsl_dcu_drm_device *fsl_dev);
fsl_dev            23 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_plane.c 	struct fsl_dcu_drm_device *fsl_dev = plane->dev->dev_private;
fsl_dev            24 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_plane.c 	unsigned int total_layer = fsl_dev->soc->total_layer;
fsl_dev            31 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_plane.c 	dev_err(fsl_dev->dev, "No more layer left\n");
fsl_dev            62 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_plane.c 	struct fsl_dcu_drm_device *fsl_dev = plane->dev->dev_private;
fsl_dev            70 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_plane.c 	regmap_read(fsl_dev->regmap, DCU_CTRLDESCLN(index, 4), &value);
fsl_dev            72 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_plane.c 	regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(index, 4), value);
fsl_dev            79 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_plane.c 	struct fsl_dcu_drm_device *fsl_dev = plane->dev->dev_private;
fsl_dev           127 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_plane.c 	regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(index, 1),
fsl_dev           130 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_plane.c 	regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(index, 2),
fsl_dev           133 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_plane.c 	regmap_write(fsl_dev->regmap,
fsl_dev           135 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_plane.c 	regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(index, 4),
fsl_dev           140 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_plane.c 	regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(index, 5),
fsl_dev           144 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_plane.c 	regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(index, 6),
fsl_dev           148 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_plane.c 	regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(index, 7), 0);
fsl_dev           149 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_plane.c 	regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(index, 8),
fsl_dev           151 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_plane.c 	regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(index, 9),
fsl_dev           154 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_plane.c 	if (!strcmp(fsl_dev->soc->name, "ls1021a")) {
fsl_dev           155 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_plane.c 		regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(index, 10),
fsl_dev           198 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_plane.c 	struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
fsl_dev           201 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_plane.c 	for (i = 0; i < fsl_dev->soc->total_layer; i++) {
fsl_dev           202 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_plane.c 		for (j = 1; j <= fsl_dev->soc->layer_regs; j++)
fsl_dev           203 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_plane.c 			regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(i, j), 0);
fsl_dev            28 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c int fsl_dcu_drm_encoder_create(struct fsl_dcu_drm_device *fsl_dev,
fsl_dev            31 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c 	struct drm_encoder *encoder = &fsl_dev->encoder;
fsl_dev            37 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c 	if (fsl_dev->tcon)
fsl_dev            38 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c 		fsl_tcon_bypass_enable(fsl_dev->tcon);
fsl_dev            40 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c 	ret = drm_encoder_init(fsl_dev->drm, encoder, &encoder_funcs,
fsl_dev            87 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c static int fsl_dcu_attach_panel(struct fsl_dcu_drm_device *fsl_dev,
fsl_dev            90 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c 	struct drm_encoder *encoder = &fsl_dev->encoder;
fsl_dev            91 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c 	struct drm_connector *connector = &fsl_dev->connector.base;
fsl_dev            94 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c 	fsl_dev->connector.encoder = encoder;
fsl_dev            96 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c 	ret = drm_connector_init(fsl_dev->drm, connector,
fsl_dev           113 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c 		dev_err(fsl_dev->dev, "failed to attach panel\n");
fsl_dev           126 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c int fsl_dcu_create_outputs(struct fsl_dcu_drm_device *fsl_dev)
fsl_dev           134 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c 	panel_node = of_parse_phandle(fsl_dev->np, "fsl,panel", 0);
fsl_dev           136 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c 		fsl_dev->connector.panel = of_drm_find_panel(panel_node);
fsl_dev           138 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c 		if (IS_ERR(fsl_dev->connector.panel))
fsl_dev           139 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c 			return PTR_ERR(fsl_dev->connector.panel);
fsl_dev           141 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c 		return fsl_dcu_attach_panel(fsl_dev, fsl_dev->connector.panel);
fsl_dev           144 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c 	ret = drm_of_find_panel_or_bridge(fsl_dev->np, 0, 0, &panel, &bridge);
fsl_dev           149 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c 		fsl_dev->connector.panel = panel;
fsl_dev           150 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c 		return fsl_dcu_attach_panel(fsl_dev, panel);
fsl_dev           153 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c 	return drm_bridge_attach(&fsl_dev->encoder, bridge, NULL);