freg              133 arch/powerpc/include/asm/exception-64e.h #define TLB_MISS_RESTORE(freg)						    \
freg              138 arch/powerpc/include/asm/exception-64e.h 	mtspr	SPRN_SPRG_TLB_EXFRAME,freg;				    \
freg              240 arch/powerpc/kernel/ptrace32.c 			unsigned long freg;
freg              241 arch/powerpc/kernel/ptrace32.c 			ret = ptrace_get_reg(child, numReg, &freg);
freg              245 arch/powerpc/kernel/ptrace32.c 				freg = (freg & ~0xfffffffful) | (data & 0xfffffffful);
freg              247 arch/powerpc/kernel/ptrace32.c 				freg = (freg & 0xfffffffful) | (data << 32);
freg              248 arch/powerpc/kernel/ptrace32.c 			ret = ptrace_put_reg(child, numReg, freg);
freg              440 arch/sparc/kernel/unaligned_64.c 	int freg;
freg              453 arch/sparc/kernel/unaligned_64.c 		freg = ((insn >> 25) & 0x1e) | ((insn >> 20) & 0x20);
freg              454 arch/sparc/kernel/unaligned_64.c 		flag = (freg < 32) ? FPRS_DL : FPRS_DU;
freg              455 arch/sparc/kernel/unaligned_64.c 		if (freg & 3) {
freg              461 arch/sparc/kernel/unaligned_64.c 			first = *(u64 *)&f->regs[freg];
freg              462 arch/sparc/kernel/unaligned_64.c 			second = *(u64 *)&f->regs[freg+2];
freg              520 arch/sparc/kernel/unaligned_64.c 			freg = (insn >> 25) & 0x1f;
freg              522 arch/sparc/kernel/unaligned_64.c 			freg = ((insn >> 25) & 0x1e) | ((insn >> 20) & 0x20);
freg              523 arch/sparc/kernel/unaligned_64.c 		flag = (freg < 32) ? FPRS_DL : FPRS_DU;
freg              558 arch/sparc/kernel/unaligned_64.c 			if (freg < 32)
freg              563 arch/sparc/kernel/unaligned_64.c 		memcpy(f->regs + freg, data, size * 4);
freg              603 arch/sparc/kernel/unaligned_64.c 	u8 freg;
freg              630 arch/sparc/kernel/unaligned_64.c 		freg = ((insn >> 25) & 0x1e) | ((insn >> 20) & 0x20);
freg              634 arch/sparc/kernel/unaligned_64.c 		flag = (freg < 32) ? FPRS_DL : FPRS_DU;
freg              640 arch/sparc/kernel/unaligned_64.c 			if (freg < 32)
freg              645 arch/sparc/kernel/unaligned_64.c 		*(u64 *)(f->regs + freg) = value;
freg              667 arch/sparc/kernel/unaligned_64.c 	u8 freg;
freg              678 arch/sparc/kernel/unaligned_64.c 		freg = ((insn >> 25) & 0x1e) | ((insn >> 20) & 0x20);
freg              680 arch/sparc/kernel/unaligned_64.c 		flag = (freg < 32) ? FPRS_DL : FPRS_DU;
freg              686 arch/sparc/kernel/unaligned_64.c 			value = *(u64 *)&f->regs[freg];
freg              283 arch/sparc/math-emu/math_32.c 	int freg;
freg              350 arch/sparc/math-emu/math_32.c 	freg = (*pfsr >> 14) & 0xf;
freg              354 arch/sparc/math-emu/math_32.c 	freg = ((insn >> 14) & 0x1f);
freg              357 arch/sparc/math-emu/math_32.c 		if (freg & 3) {				/* quadwords must have bits 4&5 of the */
freg              364 arch/sparc/math-emu/math_32.c 		if (freg & 1) {				/* doublewords must have bit 5 zeroed */
freg              369 arch/sparc/math-emu/math_32.c 	rs1 = (argp)&fregs[freg];
freg              375 arch/sparc/math-emu/math_32.c 	freg = (insn & 0x1f);
freg              378 arch/sparc/math-emu/math_32.c 		if (freg & 3) {				/* quadwords must have bits 4&5 of the */
freg              385 arch/sparc/math-emu/math_32.c 		if (freg & 1) {				/* doublewords must have bit 5 zeroed */
freg              390 arch/sparc/math-emu/math_32.c 	rs2 = (argp)&fregs[freg];
freg              396 arch/sparc/math-emu/math_32.c 	freg = ((insn >> 25) & 0x1f);
freg              399 arch/sparc/math-emu/math_32.c 		if (freg) {				/* V8 has only one set of condition codes, so */
freg              406 arch/sparc/math-emu/math_32.c 		if (freg & 3) {				/* quadwords must have bits 4&5 of the */
freg              413 arch/sparc/math-emu/math_32.c 		if (freg & 1) {				/* doublewords must have bit 5 zeroed */
freg              419 arch/sparc/math-emu/math_32.c 		rd = (void *)&fregs[freg];
freg              177 arch/sparc/math-emu/math_64.c 	int freg;
freg              299 arch/sparc/math-emu/math_64.c 				freg = ((XR >> 2) ^ XR) & 2;
freg              303 arch/sparc/math-emu/math_64.c 				case 2: if ((XR & 4) || freg) IR = 1; break;	/* Less or Equal */
freg              304 arch/sparc/math-emu/math_64.c 				case 3: if (freg) IR = 1; break;		/* Less */
freg              319 arch/sparc/math-emu/math_64.c 				freg = (insn >> 14) & 0x1f;
freg              320 arch/sparc/math-emu/math_64.c 				if (!freg)
freg              322 arch/sparc/math-emu/math_64.c 				else if (freg < 16)
freg              323 arch/sparc/math-emu/math_64.c 					XR = regs->u_regs[freg];
freg              328 arch/sparc/math-emu/math_64.c 					get_user(XR, &win32->locals[freg - 16]);
freg              333 arch/sparc/math-emu/math_64.c 					get_user(XR, &win->locals[freg - 16]);
freg              373 arch/sparc/math-emu/math_64.c 		freg = ((insn >> 14) & 0x1f);
freg              375 arch/sparc/math-emu/math_64.c 		case 3: if (freg & 2) {
freg              379 arch/sparc/math-emu/math_64.c 		case 2: freg = ((freg & 1) << 5) | (freg & 0x1e);
freg              380 arch/sparc/math-emu/math_64.c 		case 1: rs1 = (argp)&f->regs[freg];
freg              381 arch/sparc/math-emu/math_64.c 			flags = (freg < 32) ? FPRS_DL : FPRS_DU; 
freg              391 arch/sparc/math-emu/math_64.c 		freg = (insn & 0x1f);
freg              393 arch/sparc/math-emu/math_64.c 		case 3: if (freg & 2) {
freg              397 arch/sparc/math-emu/math_64.c 		case 2: freg = ((freg & 1) << 5) | (freg & 0x1e);
freg              398 arch/sparc/math-emu/math_64.c 		case 1: rs2 = (argp)&f->regs[freg];
freg              399 arch/sparc/math-emu/math_64.c 			flags = (freg < 32) ? FPRS_DL : FPRS_DU; 
freg              409 arch/sparc/math-emu/math_64.c 		freg = ((insn >> 25) & 0x1f);
freg              411 arch/sparc/math-emu/math_64.c 		case 3: if (freg & 2) {
freg              415 arch/sparc/math-emu/math_64.c 		case 2: freg = ((freg & 1) << 5) | (freg & 0x1e);
freg              416 arch/sparc/math-emu/math_64.c 		case 1: rd = (argp)&f->regs[freg];
freg              417 arch/sparc/math-emu/math_64.c 			flags = (freg < 32) ? FPRS_DL : FPRS_DU; 
freg              423 arch/sparc/math-emu/math_64.c 				if (freg < 32)
freg              498 arch/sparc/math-emu/math_64.c 				switch (freg & 3) {