frac_start        103 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c static inline u32 pll_get_cpctrl(u64 frac_start, unsigned long ref_clk,
frac_start        106 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c 	if ((frac_start != 0) || gen_ssc)
frac_start        112 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c static inline u32 pll_get_rctrl(u64 frac_start, bool gen_ssc)
frac_start        114 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c 	if ((frac_start != 0) || gen_ssc)
frac_start        120 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c static inline u32 pll_get_cctrl(u64 frac_start, bool gen_ssc)
frac_start        122 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c 	if ((frac_start != 0) || gen_ssc)
frac_start        128 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c static inline u32 pll_get_integloop_gain(u64 frac_start, u64 bclk, u32 ref_clk,
frac_start        134 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c 	if ((frac_start != 0) || gen_ssc)
frac_start        225 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c 	u64 frac_start;
frac_start        252 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c 	frac_start = pd.vco_freq * (1 << 20);
frac_start        254 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c 	rem = do_div(frac_start, pll_divisor);
frac_start        255 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c 	frac_start -= dec_start * (1 << 20);
frac_start        257 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c 		frac_start++;
frac_start        259 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c 	cpctrl = pll_get_cpctrl(frac_start, ref_clk, false);
frac_start        260 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c 	rctrl = pll_get_rctrl(frac_start, false);
frac_start        261 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c 	cctrl = pll_get_cctrl(frac_start, false);
frac_start        262 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c 	integloop_gain = pll_get_integloop_gain(frac_start, bclk,
frac_start        276 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c 	DBG("DIV_FRAC_START: %llu", frac_start);
frac_start        295 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c 	cfg->com_div_frac_start1_mode0 = (frac_start & 0xff);
frac_start        296 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c 	cfg->com_div_frac_start2_mode0 = ((frac_start & 0xff00) >> 8);
frac_start        297 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c 	cfg->com_div_frac_start3_mode0 = ((frac_start & 0xf0000) >> 16);