fp_vert_regs 313 drivers/gpu/drm/nouveau/dispnv04/dfp.c regp->fp_vert_regs[FP_DISPLAY_END] = output_mode->vdisplay - 1; fp_vert_regs 314 drivers/gpu/drm/nouveau/dispnv04/dfp.c regp->fp_vert_regs[FP_TOTAL] = output_mode->vtotal - 1; fp_vert_regs 315 drivers/gpu/drm/nouveau/dispnv04/dfp.c regp->fp_vert_regs[FP_CRTC] = output_mode->vtotal - 5 - 1; fp_vert_regs 316 drivers/gpu/drm/nouveau/dispnv04/dfp.c regp->fp_vert_regs[FP_SYNC_START] = output_mode->vsync_start - 1; fp_vert_regs 317 drivers/gpu/drm/nouveau/dispnv04/dfp.c regp->fp_vert_regs[FP_SYNC_END] = output_mode->vsync_end - 1; fp_vert_regs 318 drivers/gpu/drm/nouveau/dispnv04/dfp.c regp->fp_vert_regs[FP_VALID_START] = 0; fp_vert_regs 319 drivers/gpu/drm/nouveau/dispnv04/dfp.c regp->fp_vert_regs[FP_VALID_END] = output_mode->vdisplay - 1; fp_vert_regs 411 drivers/gpu/drm/nouveau/dispnv04/dfp.c regp->fp_vert_regs[FP_VALID_START] += diff / 2; fp_vert_regs 412 drivers/gpu/drm/nouveau/dispnv04/dfp.c regp->fp_vert_regs[FP_VALID_END] -= diff / 2; fp_vert_regs 53 drivers/gpu/drm/nouveau/dispnv04/disp.h uint32_t fp_vert_regs[7]; fp_vert_regs 426 drivers/gpu/drm/nouveau/dispnv04/hw.c regp->fp_vert_regs[i] = NVReadRAMDAC(dev, head, ramdac_reg); fp_vert_regs 504 drivers/gpu/drm/nouveau/dispnv04/hw.c NVWriteRAMDAC(dev, head, ramdac_reg, regp->fp_vert_regs[i]); fp_vert_regs 574 drivers/gpu/drm/nouveau/dispnv04/tvmodesnv17.c regs->fp_vert_regs[FP_VALID_START] = vmargin; fp_vert_regs 575 drivers/gpu/drm/nouveau/dispnv04/tvmodesnv17.c regs->fp_vert_regs[FP_VALID_END] = output_mode->vdisplay - vmargin - 1; fp_vert_regs 587 drivers/gpu/drm/nouveau/dispnv04/tvmodesnv17.c regs->fp_vert_regs[FP_VALID_START]); fp_vert_regs 589 drivers/gpu/drm/nouveau/dispnv04/tvmodesnv17.c regs->fp_vert_regs[FP_VALID_END]); fp_vert_regs 541 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c regs->fp_vert_regs[FP_DISPLAY_END] = output_mode->vdisplay - 1; fp_vert_regs 542 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c regs->fp_vert_regs[FP_TOTAL] = output_mode->vtotal - 1; fp_vert_regs 543 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c regs->fp_vert_regs[FP_SYNC_START] = fp_vert_regs 545 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c regs->fp_vert_regs[FP_SYNC_END] = output_mode->vsync_end - 1; fp_vert_regs 546 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c regs->fp_vert_regs[FP_CRTC] = output_mode->vdisplay - 1;