fp_control        108 drivers/gpu/drm/nouveau/dispnv04/dfp.c 	crtcstate[head].fp_control = FP_TG_CONTROL_OFF;
fp_control        122 drivers/gpu/drm/nouveau/dispnv04/dfp.c 		fpc = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].fp_control;
fp_control        137 drivers/gpu/drm/nouveau/dispnv04/dfp.c 			fpc = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].fp_control;
fp_control        322 drivers/gpu/drm/nouveau/dispnv04/dfp.c 	regp->fp_control = NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS |
fp_control        323 drivers/gpu/drm/nouveau/dispnv04/dfp.c 			   (savep->fp_control & (1 << 26 | NV_PRAMDAC_FP_TG_CONTROL_READ_PROG));
fp_control        327 drivers/gpu/drm/nouveau/dispnv04/dfp.c 		regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS;
fp_control        329 drivers/gpu/drm/nouveau/dispnv04/dfp.c 		regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS;
fp_control        333 drivers/gpu/drm/nouveau/dispnv04/dfp.c 		regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_MODE_CENTER;
fp_control        336 drivers/gpu/drm/nouveau/dispnv04/dfp.c 		regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_MODE_NATIVE;
fp_control        338 drivers/gpu/drm/nouveau/dispnv04/dfp.c 		regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_MODE_SCALE;
fp_control        340 drivers/gpu/drm/nouveau/dispnv04/dfp.c 		regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12;
fp_control        343 drivers/gpu/drm/nouveau/dispnv04/dfp.c 		regp->fp_control |= (2 << 24);
fp_control        355 drivers/gpu/drm/nouveau/dispnv04/dfp.c 			regp->fp_control |= (8 << 28);
fp_control        358 drivers/gpu/drm/nouveau/dispnv04/dfp.c 		regp->fp_control |= (8 << 28);
fp_control        463 drivers/gpu/drm/nouveau/dispnv04/dfp.c 	nv04_display(dev)->mode_reg.crtc_reg[head].fp_control =
fp_control         55 drivers/gpu/drm/nouveau/dispnv04/disp.h 	uint32_t fp_control;
fp_control        438 drivers/gpu/drm/nouveau/dispnv04/hw.c 	regp->fp_control = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL);
fp_control        516 drivers/gpu/drm/nouveau/dispnv04/hw.c 	NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL, regp->fp_control);
fp_control         52 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c 		fp_control, test_ctrl, dacclk, ctv_14, ctv_1c, ctv_6c;
fp_control         70 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c 	fp_control = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL);
fp_control        119 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c 	NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL, fp_control);
fp_control        548 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c 		regs->fp_control = NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS |
fp_control        553 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c 			regs->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS;
fp_control        555 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c 			regs->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS;