fp2_gen_cntl      509 drivers/gpu/drm/radeon/radeon_bios.c 	uint32_t fp2_gen_cntl;
fp2_gen_cntl      521 drivers/gpu/drm/radeon/radeon_bios.c 	fp2_gen_cntl = 0;
fp2_gen_cntl      524 drivers/gpu/drm/radeon/radeon_bios.c 		fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
fp2_gen_cntl      561 drivers/gpu/drm/radeon/radeon_bios.c 		WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON));
fp2_gen_cntl      579 drivers/gpu/drm/radeon/radeon_bios.c 		WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
fp2_gen_cntl      899 drivers/gpu/drm/radeon/radeon_legacy_encoders.c 	uint32_t fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
fp2_gen_cntl      904 drivers/gpu/drm/radeon/radeon_legacy_encoders.c 		fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN;
fp2_gen_cntl      905 drivers/gpu/drm/radeon/radeon_legacy_encoders.c 		fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
fp2_gen_cntl      910 drivers/gpu/drm/radeon/radeon_legacy_encoders.c 		fp2_gen_cntl |= RADEON_FP2_BLANK_EN;
fp2_gen_cntl      911 drivers/gpu/drm/radeon/radeon_legacy_encoders.c 		fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
fp2_gen_cntl      915 drivers/gpu/drm/radeon/radeon_legacy_encoders.c 	WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
fp2_gen_cntl      954 drivers/gpu/drm/radeon/radeon_legacy_encoders.c 	uint32_t fp2_gen_cntl;
fp2_gen_cntl      961 drivers/gpu/drm/radeon/radeon_legacy_encoders.c 		fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
fp2_gen_cntl      963 drivers/gpu/drm/radeon/radeon_legacy_encoders.c 		fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
fp2_gen_cntl      966 drivers/gpu/drm/radeon/radeon_legacy_encoders.c 			fp2_gen_cntl |= RADEON_FP2_PANEL_FORMAT; /* 24 bit format, */
fp2_gen_cntl      968 drivers/gpu/drm/radeon/radeon_legacy_encoders.c 			fp2_gen_cntl &= ~RADEON_FP2_PANEL_FORMAT;/* 18 bit format, */
fp2_gen_cntl      970 drivers/gpu/drm/radeon/radeon_legacy_encoders.c 		fp2_gen_cntl &= ~(RADEON_FP2_ON |
fp2_gen_cntl      979 drivers/gpu/drm/radeon/radeon_legacy_encoders.c 				fp2_gen_cntl |= R300_FP2_DVO_CLOCK_MODE_SINGLE;
fp2_gen_cntl      981 drivers/gpu/drm/radeon/radeon_legacy_encoders.c 				fp2_gen_cntl |= RADEON_FP2_PAD_FLOP_EN | R300_FP2_DVO_CLOCK_MODE_SINGLE;
fp2_gen_cntl      992 drivers/gpu/drm/radeon/radeon_legacy_encoders.c 			fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
fp2_gen_cntl      994 drivers/gpu/drm/radeon/radeon_legacy_encoders.c 				fp2_gen_cntl |= R200_FP2_SOURCE_SEL_RMX;
fp2_gen_cntl      996 drivers/gpu/drm/radeon/radeon_legacy_encoders.c 				fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC1;
fp2_gen_cntl      998 drivers/gpu/drm/radeon/radeon_legacy_encoders.c 			fp2_gen_cntl &= ~RADEON_FP2_SRC_SEL_CRTC2;
fp2_gen_cntl     1001 drivers/gpu/drm/radeon/radeon_legacy_encoders.c 			fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
fp2_gen_cntl     1002 drivers/gpu/drm/radeon/radeon_legacy_encoders.c 			fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
fp2_gen_cntl     1004 drivers/gpu/drm/radeon/radeon_legacy_encoders.c 			fp2_gen_cntl |= RADEON_FP2_SRC_SEL_CRTC2;
fp2_gen_cntl     1007 drivers/gpu/drm/radeon/radeon_legacy_encoders.c 	WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
fp2_gen_cntl     1043 drivers/gpu/drm/radeon/radeon_legacy_encoders.c 	uint32_t fp2_gen_cntl = 0, crtc2_gen_cntl = 0, tv_dac_cntl = 0;
fp2_gen_cntl     1051 drivers/gpu/drm/radeon/radeon_legacy_encoders.c 		fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
fp2_gen_cntl     1063 drivers/gpu/drm/radeon/radeon_legacy_encoders.c 			fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
fp2_gen_cntl     1088 drivers/gpu/drm/radeon/radeon_legacy_encoders.c 			fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
fp2_gen_cntl     1112 drivers/gpu/drm/radeon/radeon_legacy_encoders.c 		WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
fp2_gen_cntl     1162 drivers/gpu/drm/radeon/radeon_legacy_encoders.c 	uint32_t disp_hw_debug = 0, fp2_gen_cntl = 0, disp_tv_out_cntl = 0;
fp2_gen_cntl     1219 drivers/gpu/drm/radeon/radeon_legacy_encoders.c 		fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
fp2_gen_cntl     1267 drivers/gpu/drm/radeon/radeon_legacy_encoders.c 				fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
fp2_gen_cntl     1276 drivers/gpu/drm/radeon/radeon_legacy_encoders.c 				fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
fp2_gen_cntl     1278 drivers/gpu/drm/radeon/radeon_legacy_encoders.c 				fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
fp2_gen_cntl     1291 drivers/gpu/drm/radeon/radeon_legacy_encoders.c 		WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
fp2_gen_cntl     1446 drivers/gpu/drm/radeon/radeon_legacy_encoders.c 	uint32_t gpio_monid, fp2_gen_cntl, disp_output_cntl, crtc2_gen_cntl;
fp2_gen_cntl     1456 drivers/gpu/drm/radeon/radeon_legacy_encoders.c 	fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
fp2_gen_cntl     1525 drivers/gpu/drm/radeon/radeon_legacy_encoders.c 	WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
fp2_gen_cntl     1566 drivers/video/fbdev/aty/radeon_base.c 		u32 fp2_gen_cntl = INREG(FP2_GEN_CNTL);
fp2_gen_cntl     1571 drivers/video/fbdev/aty/radeon_base.c 		if ((fp2_gen_cntl & FP2_ON) == 0)
fp2_gen_cntl     1577 drivers/video/fbdev/aty/radeon_base.c 			source = (fp2_gen_cntl >> 10) & 0x3;
fp2_gen_cntl     1586 drivers/video/fbdev/aty/radeon_base.c 			source = (fp2_gen_cntl >> 13) & 0x1;
fp2_gen_cntl     1251 drivers/video/fbdev/aty/radeon_pm.c 		fp_gen_cntl, fp2_gen_cntl;
fp2_gen_cntl     1258 drivers/video/fbdev/aty/radeon_pm.c 	fp2_gen_cntl 	= INREG( FP2_GEN_CNTL);
fp2_gen_cntl     1427 drivers/video/fbdev/aty/radeon_pm.c 	OUTREG( FP2_GEN_CNTL, 		fp2_gen_cntl);
fp2_gen_cntl      217 drivers/video/fbdev/aty/radeonfb.h 	u32		fp2_gen_cntl;