force_on 34 arch/arm/mach-omap2/mcbsp.c static int omap3_mcbsp_force_ick_on(struct clk *clk, bool force_on) force_on 39 arch/arm/mach-omap2/mcbsp.c if (force_on) force_on 763 arch/x86/kernel/cpu/resctrl/core.c bool force_off, force_on; force_on 795 arch/x86/kernel/cpu/resctrl/core.c o->force_on = true; force_on 816 arch/x86/kernel/cpu/resctrl/core.c if (o->force_on) force_on 445 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c bool force_on = 1; /* disable power gating */ force_on 448 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c force_on = 0; force_on 451 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on); force_on 452 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on); force_on 453 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on); force_on 454 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on); force_on 457 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on); force_on 458 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on); force_on 459 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on); force_on 460 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on); force_on 71 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c bool force_on = 1; /* disable power gating */ force_on 74 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c force_on = 0; force_on 77 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on); force_on 78 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on); force_on 79 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on); force_on 80 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on); force_on 82 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c REG_UPDATE(DOMAIN8_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on); force_on 84 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c REG_UPDATE(DOMAIN10_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on); force_on 87 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on); force_on 88 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on); force_on 89 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on); force_on 90 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on); force_on 92 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c REG_UPDATE(DOMAIN9_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on); force_on 94 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c REG_UPDATE(DOMAIN11_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on); force_on 97 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, force_on); force_on 98 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, force_on); force_on 99 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, force_on); force_on 101 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN19_POWER_FORCEON, force_on); force_on 103 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c REG_UPDATE(DOMAIN20_PG_CONFIG, DOMAIN20_POWER_FORCEON, force_on); force_on 105 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c REG_UPDATE(DOMAIN21_PG_CONFIG, DOMAIN21_POWER_FORCEON, force_on); force_on 249 drivers/gpu/drm/gma500/power.c bool gma_power_begin(struct drm_device *dev, bool force_on) force_on 263 drivers/gpu/drm/gma500/power.c if (force_on == false) force_on 2440 drivers/gpu/drm/i915/i915_drv.c int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on) force_on 2447 drivers/gpu/drm/i915/i915_drv.c if (force_on) force_on 2451 drivers/gpu/drm/i915/i915_drv.c if (!force_on) force_on 181 drivers/iommu/intel-iommu.c static int force_on = 0; force_on 3328 drivers/iommu/intel-iommu.c if (force_on) force_on 4184 drivers/iommu/intel-iommu.c if (force_on) force_on 4263 drivers/iommu/intel-iommu.c if (force_on) force_on 4483 drivers/iommu/intel-iommu.c if (force_on) force_on 4923 drivers/iommu/intel-iommu.c force_on = tboot_force_iommu() || platform_optin_force_iommu(); force_on 4926 drivers/iommu/intel-iommu.c if (force_on) force_on 4933 drivers/iommu/intel-iommu.c if (force_on) force_on 4939 drivers/iommu/intel-iommu.c if (force_on) force_on 4987 drivers/iommu/intel-iommu.c if (force_on) force_on 4999 drivers/iommu/intel-iommu.c if (force_on) force_on 29 include/linux/platform_data/asoc-ti-mcbsp.h int (*force_ick_on)(struct clk *clk, bool force_on);