foff 88 drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c const u32 foff = buffer->id * 0x14; foff 89 drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c nvkm_mask(device, 0x100e34 + foff, 0x80000000, 0x00000000); foff 96 drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c const u32 foff = buffer->id * 0x14; foff 98 drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c nvkm_mask(device, 0x100e34 + foff, 0xc0000000, 0x40000000); foff 99 drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c nvkm_wr32(device, 0x100e28 + foff, upper_32_bits(buffer->addr)); foff 100 drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c nvkm_wr32(device, 0x100e24 + foff, lower_32_bits(buffer->addr)); foff 101 drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c nvkm_mask(device, 0x100e34 + foff, 0x80000000, 0x80000000); foff 108 drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c const u32 foff = buffer->id * 0x14; foff 110 drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c nvkm_mask(device, 0x100e34 + foff, 0x40000000, 0x40000000); foff 112 drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c buffer->entries = nvkm_rd32(device, 0x100e34 + foff) & 0x000fffff; foff 113 drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c buffer->get = 0x100e2c + foff; foff 114 drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c buffer->put = 0x100e30 + foff; foff 43 drivers/gpu/drm/nouveau/nvkm/subdev/fault/tu102.c const u32 foff = buffer->id * 0x20; foff 44 drivers/gpu/drm/nouveau/nvkm/subdev/fault/tu102.c nvkm_mask(device, 0xb83010 + foff, 0x80000000, 0x00000000); foff 51 drivers/gpu/drm/nouveau/nvkm/subdev/fault/tu102.c const u32 foff = buffer->id * 0x20; foff 53 drivers/gpu/drm/nouveau/nvkm/subdev/fault/tu102.c nvkm_mask(device, 0xb83010 + foff, 0xc0000000, 0x40000000); foff 54 drivers/gpu/drm/nouveau/nvkm/subdev/fault/tu102.c nvkm_wr32(device, 0xb83004 + foff, upper_32_bits(buffer->addr)); foff 55 drivers/gpu/drm/nouveau/nvkm/subdev/fault/tu102.c nvkm_wr32(device, 0xb83000 + foff, lower_32_bits(buffer->addr)); foff 56 drivers/gpu/drm/nouveau/nvkm/subdev/fault/tu102.c nvkm_mask(device, 0xb83010 + foff, 0x80000000, 0x80000000); foff 63 drivers/gpu/drm/nouveau/nvkm/subdev/fault/tu102.c const u32 foff = buffer->id * 0x20; foff 65 drivers/gpu/drm/nouveau/nvkm/subdev/fault/tu102.c nvkm_mask(device, 0xb83010 + foff, 0x40000000, 0x40000000); foff 67 drivers/gpu/drm/nouveau/nvkm/subdev/fault/tu102.c buffer->entries = nvkm_rd32(device, 0xb83010 + foff) & 0x000fffff; foff 68 drivers/gpu/drm/nouveau/nvkm/subdev/fault/tu102.c buffer->get = 0xb83008 + foff; foff 69 drivers/gpu/drm/nouveau/nvkm/subdev/fault/tu102.c buffer->put = 0xb8300c + foff; foff 1175 drivers/net/ethernet/sun/cassini.c val |= CAS_BASE(HP_INSTR_RAM_MID_FOFF, inst->foff); foff 2126 drivers/net/ethernet/sun/cassini.h u8 foff, fnext; /* if match fails, new offset and match */ foff 193 drivers/pinctrl/pinctrl-single.c unsigned foff; foff 1797 drivers/pinctrl/pinctrl-single.c &pcs->foff); foff 1799 drivers/pinctrl/pinctrl-single.c pcs->foff = PCS_OFF_DISABLED; foff 102 fs/nfsd/blocklayout.c bex->foff = iomap.offset; foff 108 fs/nfsd/blocklayout.c dprintk("GET: 0x%llx:0x%llx %d\n", bex->foff, bex->len, bex->es); foff 33 fs/nfsd/blocklayoutxdr.c p = xdr_encode_hyper(p, b->foff); foff 141 fs/nfsd/blocklayoutxdr.c p = xdr_decode_hyper(p, &bex.foff); foff 142 fs/nfsd/blocklayoutxdr.c if (bex.foff & (block_size - 1)) { foff 144 fs/nfsd/blocklayoutxdr.c __func__, bex.foff); foff 150 fs/nfsd/blocklayoutxdr.c __func__, bex.foff); foff 166 fs/nfsd/blocklayoutxdr.c iomaps[i].offset = bex.foff; foff 13 fs/nfsd/blocklayoutxdr.h u64 foff; foff 20 fs/nfsd/blocklayoutxdr.h u64 foff;