flush_mask 896 arch/x86/platform/uv/tlb_uv.c static int uv_flush_send_and_wait(struct cpumask *flush_mask, flush_mask 1048 arch/x86/platform/uv/tlb_uv.c static int set_distrib_bits(struct cpumask *flush_mask, struct bau_control *bcp, flush_mask 1056 arch/x86/platform/uv/tlb_uv.c for_each_cpu(cpu, flush_mask) { flush_mask 1108 arch/x86/platform/uv/tlb_uv.c struct cpumask *flush_mask; flush_mask 1144 arch/x86/platform/uv/tlb_uv.c flush_mask = (struct cpumask *)per_cpu(uv_flush_tlb_mask, cpu); flush_mask 1146 arch/x86/platform/uv/tlb_uv.c cpumask_andnot(flush_mask, cpumask, cpumask_of(cpu)); flush_mask 1154 arch/x86/platform/uv/tlb_uv.c if (set_distrib_bits(flush_mask, bcp, bau_desc, &locals, &remotes)) flush_mask 1182 arch/x86/platform/uv/tlb_uv.c if (!uv_flush_send_and_wait(flush_mask, bcp, bau_desc)) flush_mask 127 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c u32 flush_mask; flush_mask 140 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c dpu_plane_get_ctl_flush(plane, ctl, &flush_mask); flush_mask 171 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c mixer[lm_idx].flush_mask |= flush_mask; flush_mask 205 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c mixer[i].flush_mask = 0; flush_mask 222 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c mixer[i].flush_mask |= ctl->ops.get_bitmask_mixer(ctl, flush_mask 226 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c ctl->ops.update_pending_flush(ctl, mixer[i].flush_mask); flush_mask 232 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c mixer[i].flush_mask); flush_mask 83 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h u32 flush_mask; flush_mask 471 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c u32 flush_mask = 0; flush_mask 486 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c ctl->ops.get_bitmask_intf(ctl, &flush_mask, phys_enc->intf_idx); flush_mask 487 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c ctl->ops.update_pending_flush(ctl, flush_mask); flush_mask 437 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c u32 flush_mask = 0; flush_mask 459 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c ctl->ops.get_bitmask_intf(ctl, &flush_mask, phys_enc->hw_intf->idx); flush_mask 460 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c ctl->ops.update_pending_flush(ctl, flush_mask); flush_mask 465 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c ctl->idx - CTL_0, flush_mask); flush_mask 87 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c static u32 crtc_flush(struct drm_crtc *crtc, u32 flush_mask) flush_mask 96 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c DBG("%s: flush=%08x", crtc->name, flush_mask); flush_mask 98 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c return mdp5_ctl_commit(ctl, pipeline, flush_mask, start); flush_mask 111 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c uint32_t flush_mask = 0; flush_mask 120 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c flush_mask |= mdp5_plane_get_flush(plane); flush_mask 124 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c flush_mask |= mdp_ctl_flush_mask_lm(mixer->lm); flush_mask 128 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c flush_mask |= mdp_ctl_flush_mask_lm(r_mixer->lm); flush_mask 130 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c return crtc_flush(crtc, flush_mask); flush_mask 869 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c uint32_t flush_mask = mdp_ctl_flush_mask_cursor(0); flush_mask 930 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c crtc_flush(crtc, flush_mask); flush_mask 947 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c uint32_t flush_mask = mdp_ctl_flush_mask_cursor(0); flush_mask 979 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c crtc_flush(crtc, flush_mask); flush_mask 38 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c u32 flush_mask; flush_mask 471 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c u32 flush_mask) flush_mask 476 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c (!(ctl_mgr->flush_hw_mask & bit) && (flush_mask & bit)) flush_mask 485 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c static void fix_for_single_flush(struct mdp5_ctl *ctl, u32 *flush_mask, flush_mask 491 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c DBG("CTL %d FLUSH pending mask %x", ctl->id, *flush_mask); flush_mask 493 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c ctl_mgr->single_flush_pending_mask |= (*flush_mask); flush_mask 494 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c *flush_mask = 0; flush_mask 498 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c *flush_mask = ctl_mgr->single_flush_pending_mask; flush_mask 504 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c DBG("Single FLUSH mask %x,ID %d", *flush_mask, flush_mask 528 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c u32 flush_mask, bool start) flush_mask 535 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c VERB("flush_mask=%x, trigger=%x", flush_mask, ctl->pending_ctl_trigger); flush_mask 537 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c if (ctl->pending_ctl_trigger & flush_mask) { flush_mask 538 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c flush_mask |= MDP5_CTL_FLUSH_CTL; flush_mask 542 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c flush_mask |= fix_sw_flush(ctl, pipeline, flush_mask); flush_mask 544 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c flush_mask &= ctl_mgr->flush_hw_mask; flush_mask 546 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c curr_ctl_flush_mask = flush_mask; flush_mask 548 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c fix_for_single_flush(ctl, &flush_mask, &flush_id); flush_mask 551 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c ctl->flush_mask |= flush_mask; flush_mask 554 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c flush_mask |= ctl->flush_mask; flush_mask 555 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c ctl->flush_mask = 0; flush_mask 558 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c if (flush_mask) { flush_mask 560 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c ctl_write(ctl, REG_MDP5_CTL_FLUSH(flush_id), flush_mask); flush_mask 73 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.h u32 flush_mask, bool start); flush_mask 158 drivers/gpu/drm/msm/disp/mdp5/mdp5_mixer.c mixer->flush_mask = mdp_ctl_flush_mask_lm(lm->id); flush_mask 20 drivers/gpu/drm/msm/disp/mdp5/mdp5_mixer.h uint32_t flush_mask; /* used to commit LM registers */ flush_mask 164 drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.c hwpipe->flush_mask = mdp_ctl_flush_mask_pipe(pipe); flush_mask 23 drivers/gpu/drm/msm/disp/mdp5/mdp5_pipe.h uint32_t flush_mask; /* used to commit pipe registers */ flush_mask 1057 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mask = pstate->hwpipe->flush_mask; flush_mask 1060 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mask |= pstate->r_hwpipe->flush_mask;