flush_hw_mask      36 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 		.flush_hw_mask = 0x0003ffff,
flush_hw_mask     120 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 		.flush_hw_mask = 0x0003ffff,
flush_hw_mask     210 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 		.flush_hw_mask = 0x003fffff,
flush_hw_mask     297 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 		.flush_hw_mask = 0x4003ffff,
flush_hw_mask     372 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 		.flush_hw_mask = 0xf0ffffff,
flush_hw_mask     452 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 		.flush_hw_mask = 0xf4ffffff,
flush_hw_mask     557 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 		.flush_hw_mask = 0xffffffff,
flush_hw_mask     645 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 		.flush_hw_mask = 0xf7ffffff,
flush_hw_mask      56 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.h 	uint32_t flush_hw_mask;		/* FLUSH register's hardware mask */
flush_hw_mask      63 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c 	u32 flush_hw_mask;
flush_hw_mask     476 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c 	(!(ctl_mgr->flush_hw_mask & bit) && (flush_mask & bit))
flush_hw_mask     544 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c 	flush_mask &= ctl_mgr->flush_hw_mask;
flush_hw_mask     709 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c 	ctl_mgr->flush_hw_mask = ctl_cfg->flush_hw_mask;