first_vid        2741 drivers/infiniband/hw/mlx5/main.c 				 first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
first_vid        2743 drivers/infiniband/hw/mlx5/main.c 				 first_vid, ntohs(ib_spec->eth.val.vlan_tag));
first_vid         144 drivers/net/ethernet/mellanox/mlx5/core/diag/fs_tracepoint.c 	PRINT_MASKED_VAL_L2(u16, first_vid, first_vid, p, "%04x");
first_vid         204 drivers/net/ethernet/mellanox/mlx5/core/en_fs.c 				 outer_headers.first_vid);
first_vid         205 drivers/net/ethernet/mellanox/mlx5/core/en_fs.c 		MLX5_SET(fte_match_param, spec->match_value, outer_headers.first_vid,
first_vid         214 drivers/net/ethernet/mellanox/mlx5/core/en_fs.c 				 outer_headers.first_vid);
first_vid         215 drivers/net/ethernet/mellanox/mlx5/core/en_fs.c 		MLX5_SET(fte_match_param, spec->match_value, outer_headers.first_vid,
first_vid        1405 drivers/net/ethernet/mellanox/mlx5/core/en_fs.c 	MLX5_SET_TO_ONES(fte_match_param, mc, outer_headers.first_vid);
first_vid        1417 drivers/net/ethernet/mellanox/mlx5/core/en_fs.c 	MLX5_SET_TO_ONES(fte_match_param, mc, outer_headers.first_vid);
first_vid         310 drivers/net/ethernet/mellanox/mlx5/core/en_fs_ethtool.c 	MLX5E_FTE_SET(headers_c, first_vid, 0xfff);
first_vid         311 drivers/net/ethernet/mellanox/mlx5/core/en_fs_ethtool.c 	MLX5E_FTE_SET(headers_v, first_vid, ntohs(vlan_tci));
first_vid        1904 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c 			MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid,
first_vid        1906 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c 			MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid,
first_vid        2296 drivers/net/ethernet/mellanox/mlx5/core/en_tc.c 	OFFLOAD(FIRST_VID,  2, vlan.h_vlan_TCI, 0, first_vid),
first_vid        1005 drivers/net/ethernet/mellanox/mlx5/core/eswitch.c 	MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.first_vid);
first_vid        1370 drivers/net/ethernet/mellanox/mlx5/core/eswitch.c 	MLX5_SET_TO_ONES(fte_match_param, spec->match_criteria, outer_headers.first_vid);
first_vid        1371 drivers/net/ethernet/mellanox/mlx5/core/eswitch.c 	MLX5_SET(fte_match_param, spec->match_value, outer_headers.first_vid, vport->info.vlan);
first_vid        1896 drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c 	MLX5_SET_TO_ONES(fte_match_param, spec->match_criteria, outer_headers.first_vid);
first_vid        1897 drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c 	MLX5_SET(fte_match_param, spec->match_value, outer_headers.first_vid, 0);
first_vid          62 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c #define DR_MASK_IS_L2_DST(_spec, _misc, _inner_outer) (_spec.first_vid || \
first_vid         790 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c 	DR_STE_SET_MASK_V(eth_l2_src_dst, bit_mask, first_vlan_id, mask, first_vid);
first_vid         876 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c 	spec->first_vid = MLX5_GET(fte_match_set_lyr_2_4, mask, first_vid);
first_vid        1086 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c 	DR_STE_SET_TAG(eth_l2_src_dst, tag, first_vlan_id, spec, first_vid);
first_vid        1279 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c 	DR_STE_SET_MASK_V(eth_l2_src, bit_mask, first_vlan_id, mask, first_vid);
first_vid        1331 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c 	DR_STE_SET_TAG(eth_l2_src, tag, first_vlan_id, spec, first_vid);
first_vid        1469 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c 	DR_STE_SET_MASK_V(eth_l2_tnl, bit_mask, first_vlan_id, mask, first_vid);
first_vid        1500 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c 	DR_STE_SET_TAG(eth_l2_tnl, tag, first_vlan_id, spec, first_vid);
first_vid         361 drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h 	u32 first_vid:12;
first_vid         453 include/linux/mlx5/mlx5_ifc.h 	u8         first_vid[0xc];