first_pipe       1952 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].prev_odm_pipe;
first_pipe       1954 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			while (first_pipe->prev_odm_pipe)
first_pipe       1955 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 				first_pipe = first_pipe->prev_odm_pipe;
first_pipe       1956 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			pipes[pipe_cnt].pipe.src.hsplit_grp = first_pipe->pipe_idx;
first_pipe       13357 drivers/gpu/drm/i915/display/intel_display.c 	enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
first_pipe       13371 drivers/gpu/drm/i915/display/intel_display.c 			first_pipe = crtc->pipe;
first_pipe       13401 drivers/gpu/drm/i915/display/intel_display.c 		other_crtc_state->hsw_workaround_pipe = first_pipe;