first_line_bpg_offset 277 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c DC_LOG_DSC("\tfirst_line_bpg_offset %d", pps->first_line_bpg_offset); first_line_bpg_offset 591 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c FIRST_LINE_BPG_OFFSET, reg_vals->pps.first_line_bpg_offset, first_line_bpg_offset 192 drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c rc->first_line_bpg_offset = median3(0, (12 + (int) (0.09 * min(34, slice_height - 8))), (int)((3 * bpc * 3) - (3 * bpp_group))); first_line_bpg_offset 197 drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c rc->first_line_bpg_offset = median3(0, (12 + (int) (0.09 * min(34, slice_height - 8))), (int)((3 * bpc * 4) - (3 * bpp_group))); first_line_bpg_offset 203 drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c rc->first_line_bpg_offset = median3(0, (12 + (int) (0.09 * min(34, slice_height - 8))), (int)(((3 * bpc + (cm == CM_444 ? 0 : 2)) * 3) - (3 * bpp_group))); first_line_bpg_offset 41 drivers/gpu/drm/amd/display/dc/dsc/rc_calc.h int first_line_bpg_offset; first_line_bpg_offset 54 drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c to->first_line_bpg_offset = from->first_line_bpg_offset; first_line_bpg_offset 83 drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c dsc_cfg->first_line_bpg_offset = rc->first_line_bpg_offset; first_line_bpg_offset 164 drivers/gpu/drm/drm_dsc.c pps_payload->first_line_bpg_offset = first_line_bpg_offset 165 drivers/gpu/drm/drm_dsc.c dsc_cfg->first_line_bpg_offset; first_line_bpg_offset 334 drivers/gpu/drm/drm_dsc.c vdsc_cfg->nfl_bpg_offset = DIV_ROUND_UP((vdsc_cfg->first_line_bpg_offset << 11), first_line_bpg_offset 387 drivers/gpu/drm/drm_dsc.c groups_per_line * vdsc_cfg->first_line_bpg_offset; first_line_bpg_offset 43 drivers/gpu/drm/i915/display/intel_vdsc.c u8 first_line_bpg_offset; first_line_bpg_offset 409 drivers/gpu/drm/i915/display/intel_vdsc.c vdsc_cfg->first_line_bpg_offset = first_line_bpg_offset 410 drivers/gpu/drm/i915/display/intel_vdsc.c rc_params[row_index][column_index].first_line_bpg_offset; first_line_bpg_offset 628 drivers/gpu/drm/i915/display/intel_vdsc.c DSC_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset) | first_line_bpg_offset 168 include/drm/drm_dsc.h u8 first_line_bpg_offset; first_line_bpg_offset 427 include/drm/drm_dsc.h u8 first_line_bpg_offset;