fine_val          136 drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c 	u32 delay_val = 0, fine_val = 0;
fine_val          179 drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c 			fine_val = ETH_RMII_DLY_TX_INV;
fine_val          185 drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c 		fine_val = ETH_FINE_DLY_GTXC | ETH_FINE_DLY_RXC;
fine_val          200 drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c 	regmap_write(plat->peri_regmap, PERI_ETH_DLY_FINE, fine_val);