final_offset      281 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	DC_LOG_DSC("\tfinal_offset %d", pps->final_offset);
final_offset      487 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	reg_vals->pps.final_offset                = 0;
final_offset      604 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 		FINAL_OFFSET, reg_vals->pps.final_offset);
final_offset       68 drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c 	to->final_offset             = from->final_offset;
final_offset      180 drivers/gpu/drm/drm_dsc.c 	pps_payload->final_offset = cpu_to_be16(dsc_cfg->final_offset);
final_offset      317 drivers/gpu/drm/drm_dsc.c 	vdsc_cfg->final_offset = vdsc_cfg->rc_model_size -
final_offset      321 drivers/gpu/drm/drm_dsc.c 	if (vdsc_cfg->final_offset >= vdsc_cfg->rc_model_size) {
final_offset      327 drivers/gpu/drm/drm_dsc.c 		(vdsc_cfg->rc_model_size - vdsc_cfg->final_offset);
final_offset      362 drivers/gpu/drm/drm_dsc.c 				(vdsc_cfg->final_offset * (1 << 11)) /
final_offset      669 drivers/gpu/drm/i915/display/intel_vdsc.c 	pps_val |= DSC_FINAL_OFFSET(vdsc_cfg->final_offset) |
final_offset     11378 drivers/gpu/drm/i915/i915_reg.h #define  DSC_FINAL_OFFSET(final_offset)			((final_offset) << 0)
final_offset      222 include/drm/drm_dsc.h 	u16 final_offset;
final_offset      449 include/drm/drm_dsc.h 	__be16 final_offset;