fifo_val           19 drivers/gpu/drm/nouveau/include/nvkm/engine/xtensa.h 	u32 fifo_val;
fifo_val           30 drivers/gpu/drm/nouveau/nvkm/engine/bsp/g84.c 	.fifo_val = 0x1111,
fifo_val           30 drivers/gpu/drm/nouveau/nvkm/engine/vp/g84.c 	.fifo_val = 0x111,
fifo_val           74 drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c 		nvkm_mask(device, xtensa->addr + 0xd94, 0, xtensa->func->fifo_val);
fifo_val          348 drivers/iio/adc/meson_saradc.c 	int regval, fifo_chan, fifo_val, count;
fifo_val          370 drivers/iio/adc/meson_saradc.c 	fifo_val = FIELD_GET(MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK, regval);
fifo_val          371 drivers/iio/adc/meson_saradc.c 	fifo_val &= GENMASK(priv->param->resolution - 1, 0);
fifo_val          372 drivers/iio/adc/meson_saradc.c 	*val = meson_sar_adc_calib_val(indio_dev, fifo_val);