fifo_state 715 drivers/gpu/drm/i915/display/intel_display_types.h struct vlv_fifo_state fifo_state; fifo_state 497 drivers/gpu/drm/i915/intel_pm.c struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state; fifo_state 526 drivers/gpu/drm/i915/intel_pm.c fifo_state->plane[PLANE_PRIMARY] = sprite0_start; fifo_state 527 drivers/gpu/drm/i915/intel_pm.c fifo_state->plane[PLANE_SPRITE0] = sprite1_start - sprite0_start; fifo_state 528 drivers/gpu/drm/i915/intel_pm.c fifo_state->plane[PLANE_SPRITE1] = 511 - sprite1_start; fifo_state 529 drivers/gpu/drm/i915/intel_pm.c fifo_state->plane[PLANE_CURSOR] = 63; fifo_state 1668 drivers/gpu/drm/i915/intel_pm.c struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state; fifo_state 1703 drivers/gpu/drm/i915/intel_pm.c fifo_state->plane[plane_id] = 0; fifo_state 1708 drivers/gpu/drm/i915/intel_pm.c fifo_state->plane[plane_id] = fifo_size * rate / total_rate; fifo_state 1709 drivers/gpu/drm/i915/intel_pm.c fifo_left -= fifo_state->plane[plane_id]; fifo_state 1712 drivers/gpu/drm/i915/intel_pm.c fifo_state->plane[PLANE_SPRITE0] += sprite0_fifo_extra; fifo_state 1715 drivers/gpu/drm/i915/intel_pm.c fifo_state->plane[PLANE_CURSOR] = 63; fifo_state 1730 drivers/gpu/drm/i915/intel_pm.c fifo_state->plane[plane_id] += plane_extra; fifo_state 1739 drivers/gpu/drm/i915/intel_pm.c fifo_state->plane[PLANE_PRIMARY] = fifo_left; fifo_state 1836 drivers/gpu/drm/i915/intel_pm.c const struct vlv_fifo_state *fifo_state = fifo_state 1837 drivers/gpu/drm/i915/intel_pm.c &crtc_state->wm.vlv.fifo_state; fifo_state 1839 drivers/gpu/drm/i915/intel_pm.c return raw->plane[plane_id] <= fifo_state->plane[plane_id]; fifo_state 1857 drivers/gpu/drm/i915/intel_pm.c const struct vlv_fifo_state *fifo_state = fifo_state 1858 drivers/gpu/drm/i915/intel_pm.c &crtc_state->wm.vlv.fifo_state; fifo_state 1897 drivers/gpu/drm/i915/intel_pm.c &old_crtc_state->wm.vlv.fifo_state; fifo_state 1904 drivers/gpu/drm/i915/intel_pm.c memcmp(old_fifo_state, fifo_state, fifo_state 1905 drivers/gpu/drm/i915/intel_pm.c sizeof(*fifo_state)) != 0) fifo_state 1928 drivers/gpu/drm/i915/intel_pm.c fifo_state->plane[plane_id]); fifo_state 1963 drivers/gpu/drm/i915/intel_pm.c const struct vlv_fifo_state *fifo_state = fifo_state 1964 drivers/gpu/drm/i915/intel_pm.c &crtc_state->wm.vlv.fifo_state; fifo_state 1970 drivers/gpu/drm/i915/intel_pm.c sprite0_start = fifo_state->plane[PLANE_PRIMARY]; fifo_state 1971 drivers/gpu/drm/i915/intel_pm.c sprite1_start = fifo_state->plane[PLANE_SPRITE0] + sprite0_start; fifo_state 1972 drivers/gpu/drm/i915/intel_pm.c fifo_size = fifo_state->plane[PLANE_SPRITE1] + sprite1_start; fifo_state 1974 drivers/gpu/drm/i915/intel_pm.c WARN_ON(fifo_state->plane[PLANE_CURSOR] != 63); fifo_state 6175 drivers/gpu/drm/i915/intel_pm.c const struct vlv_fifo_state *fifo_state = fifo_state 6176 drivers/gpu/drm/i915/intel_pm.c &crtc_state->wm.vlv.fifo_state; fifo_state 6199 drivers/gpu/drm/i915/intel_pm.c fifo_state->plane[plane_id]); fifo_state 6238 drivers/gpu/drm/i915/intel_pm.c const struct vlv_fifo_state *fifo_state = fifo_state 6239 drivers/gpu/drm/i915/intel_pm.c &crtc_state->wm.vlv.fifo_state; fifo_state 6254 drivers/gpu/drm/i915/intel_pm.c fifo_state->plane[plane_id]); fifo_state 1034 drivers/gpu/drm/vmwgfx/vmwgfx_drv.h struct vmw_fifo_state *fifo_state); fifo_state 302 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c struct vmw_fifo_state *fifo_state = &dev_priv->fifo; fifo_state 307 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c uint32_t reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE; fifo_state 310 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c mutex_lock(&fifo_state->fifo_mutex); fifo_state 318 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c BUG_ON(fifo_state->reserved_size != 0); fifo_state 319 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c BUG_ON(fifo_state->dynamic_buffer != NULL); fifo_state 321 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c fifo_state->reserved_size = bytes; fifo_state 355 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c fifo_state->using_bounce_buffer = false; fifo_state 368 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c fifo_state->using_bounce_buffer = true; fifo_state 369 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c if (bytes < fifo_state->static_buffer_size) fifo_state 370 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c return fifo_state->static_buffer; fifo_state 372 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c fifo_state->dynamic_buffer = vmalloc(bytes); fifo_state 373 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c if (!fifo_state->dynamic_buffer) fifo_state 375 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c return fifo_state->dynamic_buffer; fifo_state 380 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c fifo_state->reserved_size = 0; fifo_state 381 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c mutex_unlock(&fifo_state->fifo_mutex); fifo_state 406 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c static void vmw_fifo_res_copy(struct vmw_fifo_state *fifo_state, fifo_state 413 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ? fifo_state 414 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c fifo_state->dynamic_buffer : fifo_state->static_buffer; fifo_state 427 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c static void vmw_fifo_slow_copy(struct vmw_fifo_state *fifo_state, fifo_state 432 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ? fifo_state 433 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c fifo_state->dynamic_buffer : fifo_state->static_buffer; fifo_state 449 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c struct vmw_fifo_state *fifo_state = &dev_priv->fifo; fifo_state 454 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c bool reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE; fifo_state 456 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c if (fifo_state->dx) fifo_state 459 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c fifo_state->dx = false; fifo_state 461 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c BUG_ON(bytes > fifo_state->reserved_size); fifo_state 463 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c fifo_state->reserved_size = 0; fifo_state 465 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c if (fifo_state->using_bounce_buffer) { fifo_state 467 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c vmw_fifo_res_copy(fifo_state, fifo_mem, fifo_state 470 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c vmw_fifo_slow_copy(fifo_state, fifo_mem, fifo_state 473 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c if (fifo_state->dynamic_buffer) { fifo_state 474 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c vfree(fifo_state->dynamic_buffer); fifo_state 475 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c fifo_state->dynamic_buffer = NULL; fifo_state 480 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c down_write(&fifo_state->rwsem); fifo_state 481 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c if (fifo_state->using_bounce_buffer || reserveable) { fifo_state 492 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c up_write(&fifo_state->rwsem); fifo_state 494 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c mutex_unlock(&fifo_state->fifo_mutex); fifo_state 539 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c struct vmw_fifo_state *fifo_state = &dev_priv->fifo; fifo_state 558 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c if (!(fifo_state->capabilities & SVGA_FIFO_CAP_FENCE)) { fifo_state 573 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c (void) vmw_marker_push(&fifo_state->marker_queue, *seqno); fifo_state 574 drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c vmw_update_seqno(dev_priv, fifo_state); fifo_state 118 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c struct vmw_fifo_state *fifo_state) fifo_state 125 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c vmw_marker_pull(&fifo_state->marker_queue, seqno); fifo_state 133 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c struct vmw_fifo_state *fifo_state; fifo_state 139 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c fifo_state = &dev_priv->fifo; fifo_state 140 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c vmw_update_seqno(dev_priv, fifo_state); fifo_state 144 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c if (!(fifo_state->capabilities & SVGA_FIFO_CAP_FENCE) && fifo_state 166 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c struct vmw_fifo_state *fifo_state = &dev_priv->fifo; fifo_state 183 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c down_read(&fifo_state->rwsem); fifo_state 233 drivers/gpu/drm/vmwgfx/vmwgfx_irq.c up_read(&fifo_state->rwsem); fifo_state 324 drivers/isdn/hardware/mISDN/hfcpci.c u_char fifo_state; fifo_state 329 drivers/isdn/hardware/mISDN/hfcpci.c fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B2RX; fifo_state 332 drivers/isdn/hardware/mISDN/hfcpci.c fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B1RX; fifo_state 334 drivers/isdn/hardware/mISDN/hfcpci.c if (fifo_state) fifo_state 335 drivers/isdn/hardware/mISDN/hfcpci.c hc->hw.fifo_en ^= fifo_state; fifo_state 343 drivers/isdn/hardware/mISDN/hfcpci.c if (fifo_state) fifo_state 344 drivers/isdn/hardware/mISDN/hfcpci.c hc->hw.fifo_en |= fifo_state; fifo_state 353 drivers/isdn/hardware/mISDN/hfcpci.c u_char fifo_state; fifo_state 358 drivers/isdn/hardware/mISDN/hfcpci.c fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B2TX; fifo_state 361 drivers/isdn/hardware/mISDN/hfcpci.c fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B1TX; fifo_state 363 drivers/isdn/hardware/mISDN/hfcpci.c if (fifo_state) fifo_state 364 drivers/isdn/hardware/mISDN/hfcpci.c hc->hw.fifo_en ^= fifo_state; fifo_state 372 drivers/isdn/hardware/mISDN/hfcpci.c fifo_state); fifo_state 377 drivers/isdn/hardware/mISDN/hfcpci.c if (fifo_state) fifo_state 378 drivers/isdn/hardware/mISDN/hfcpci.c hc->hw.fifo_en |= fifo_state; fifo_state 662 drivers/net/ethernet/cavium/thunder/nicvf_queues.c u64 tmp, fifo_state; fifo_state 676 drivers/net/ethernet/cavium/thunder/nicvf_queues.c fifo_state = nicvf_queue_reg_read(nic, NIC_QSET_RBDR_0_1_STATUS0, qidx); fifo_state 677 drivers/net/ethernet/cavium/thunder/nicvf_queues.c if (((fifo_state >> 62) & 0x03) == 0x3)