field_ddc_fifo_tx_thres 220 drivers/gpu/drm/sun4i/sun4i_hdmi.h struct reg_field field_ddc_fifo_tx_thres; field_ddc_fifo_tx_thres 280 drivers/gpu/drm/sun4i/sun4i_hdmi.h struct regmap_field *field_ddc_fifo_tx_thres; field_ddc_fifo_tx_thres 363 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c .field_ddc_fifo_tx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 0, 3), field_ddc_fifo_tx_thres 414 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c .field_ddc_fifo_tx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 0, 3), field_ddc_fifo_tx_thres 471 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c .field_ddc_fifo_tx_thres = REG_FIELD(SUN6I_HDMI_DDC_FIFO_CTRL_REG, 0, 3), field_ddc_fifo_tx_thres 97 drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c regmap_field_write(hdmi->field_ddc_fifo_tx_thres, field_ddc_fifo_tx_thres 254 drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c hdmi->field_ddc_fifo_tx_thres = field_ddc_fifo_tx_thres 256 drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c hdmi->variant->field_ddc_fifo_tx_thres); field_ddc_fifo_tx_thres 257 drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c if (IS_ERR(hdmi->field_ddc_fifo_tx_thres)) field_ddc_fifo_tx_thres 258 drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c return PTR_ERR(hdmi->field_ddc_fifo_tx_thres);