field_ddc_fifo_rx_thres  219 drivers/gpu/drm/sun4i/sun4i_hdmi.h 	struct reg_field	field_ddc_fifo_rx_thres;
field_ddc_fifo_rx_thres  279 drivers/gpu/drm/sun4i/sun4i_hdmi.h 	struct regmap_field	*field_ddc_fifo_rx_thres;
field_ddc_fifo_rx_thres  362 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c 	.field_ddc_fifo_rx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 4, 7),
field_ddc_fifo_rx_thres  413 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c 	.field_ddc_fifo_rx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 4, 7),
field_ddc_fifo_rx_thres  470 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c 	.field_ddc_fifo_rx_thres = REG_FIELD(SUN6I_HDMI_DDC_FIFO_CTRL_REG, 4, 7),
field_ddc_fifo_rx_thres   99 drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c 	regmap_field_write(hdmi->field_ddc_fifo_rx_thres, RX_THRESHOLD);
field_ddc_fifo_rx_thres  248 drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c 	hdmi->field_ddc_fifo_rx_thres =
field_ddc_fifo_rx_thres  250 drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c 					hdmi->variant->field_ddc_fifo_rx_thres);
field_ddc_fifo_rx_thres  251 drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c 	if (IS_ERR(hdmi->field_ddc_fifo_rx_thres))
field_ddc_fifo_rx_thres  252 drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c 		return PTR_ERR(hdmi->field_ddc_fifo_rx_thres);