fgi               335 drivers/net/can/m_can/m_can.c 			   u32 fgi, unsigned int offset)
fgi               337 drivers/net/can/m_can/m_can.c 	u32 addr_offset = cdev->mcfg[MRAM_RXF0].off + fgi * RXF0_ELEMENT_SIZE +
fgi               358 drivers/net/can/m_can/m_can.c static u32 m_can_txe_fifo_read(struct m_can_classdev *cdev, u32 fgi, u32 offset)
fgi               360 drivers/net/can/m_can/m_can.c 	u32 addr_offset = cdev->mcfg[MRAM_TXE].off + fgi * TXE_ELEMENT_SIZE +
fgi               443 drivers/net/can/m_can/m_can.c 	u32 id, fgi, dlc;
fgi               447 drivers/net/can/m_can/m_can.c 	fgi = (rxfs & RXFS_FGI_MASK) >> RXFS_FGI_SHIFT;
fgi               448 drivers/net/can/m_can/m_can.c 	dlc = m_can_fifo_read(cdev, fgi, M_CAN_FIFO_DLC);
fgi               463 drivers/net/can/m_can/m_can.c 	id = m_can_fifo_read(cdev, fgi, M_CAN_FIFO_ID);
fgi               482 drivers/net/can/m_can/m_can.c 				m_can_fifo_read(cdev, fgi,
fgi               487 drivers/net/can/m_can/m_can.c 	m_can_write(cdev, M_CAN_RXF0A, fgi);
fgi               875 drivers/net/can/m_can/m_can.c 	u32 fgi = 0;
fgi               892 drivers/net/can/m_can/m_can.c 		fgi = (m_can_read(cdev, M_CAN_TXEFS) & TXEFS_EFGI_MASK)
fgi               896 drivers/net/can/m_can/m_can.c 		msg_mark = (m_can_txe_fifo_read(cdev, fgi, 4) &
fgi               901 drivers/net/can/m_can/m_can.c 						(fgi << TXEFA_EFAI_SHIFT)));