fence_num         193 drivers/gpu/drm/i915/gvt/handlers.c 		unsigned int fence_num, void *p_data, unsigned int bytes)
fence_num         197 drivers/gpu/drm/i915/gvt/handlers.c 	if (fence_num >= max_fence) {
fence_num         199 drivers/gpu/drm/i915/gvt/handlers.c 			     fence_num, max_fence);
fence_num         257 drivers/gpu/drm/i915/gvt/handlers.c 	unsigned int fence_num = offset_to_fence_num(off);
fence_num         260 drivers/gpu/drm/i915/gvt/handlers.c 	ret = sanitize_fence_mmio_access(vgpu, fence_num, p_data, bytes);
fence_num         266 drivers/gpu/drm/i915/gvt/handlers.c 	intel_vgpu_write_fence(vgpu, fence_num,
fence_num         267 drivers/gpu/drm/i915/gvt/handlers.c 			vgpu_vreg64(vgpu, fence_num_to_offset(fence_num)));
fence_num        1190 drivers/gpu/drm/i915/gvt/handlers.c 		_vgtif_reg(avail_rs.fence_num):
fence_num        1192 drivers/gpu/drm/i915/gvt/handlers.c 			_vgtif_reg(avail_rs.fence_num) + 4)
fence_num          60 drivers/gpu/drm/i915/gvt/vgpu.c 	vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.fence_num)) = vgpu_fence_sz(vgpu);
fence_num         843 drivers/gpu/drm/i915/i915_gem_fence_reg.c 					       vgtif_reg(avail_rs.fence_num));
fence_num          86 drivers/gpu/drm/i915/i915_pvinfo.h 		u32 fence_num;