fec_cap          3102 drivers/gpu/drm/amd/display/dc/core/dc_link.c 	if (link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) {
fec_cap          2910 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 	memset(&link->dpcd_caps.fec_cap, '\0', sizeof(link->dpcd_caps.fec_cap));
fec_cap          2916 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 				&link->dpcd_caps.fec_cap.raw,
fec_cap          2917 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 				sizeof(link->dpcd_caps.fec_cap.raw));
fec_cap          3468 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 			link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) {
fec_cap          3504 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 			link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) {
fec_cap           960 drivers/gpu/drm/amd/display/dc/dc.h 	union dpcd_fec_capability fec_cap;
fec_cap           413 drivers/net/ethernet/mellanox/mlx5/core/en/port.c 				   u8 *fec_cap,
fec_cap           419 drivers/net/ethernet/mellanox/mlx5/core/en/port.c 		*fec_cap = MLX5_GET(pplm_reg, pplm,
fec_cap           423 drivers/net/ethernet/mellanox/mlx5/core/en/port.c 		*fec_cap = MLX5_GET(pplm_reg, pplm,
fec_cap           427 drivers/net/ethernet/mellanox/mlx5/core/en/port.c 		*fec_cap = MLX5_GET(pplm_reg, pplm,
fec_cap           431 drivers/net/ethernet/mellanox/mlx5/core/en/port.c 		*fec_cap = MLX5_GET(pplm_reg, pplm,
fec_cap           435 drivers/net/ethernet/mellanox/mlx5/core/en/port.c 		*fec_cap = MLX5_GET(pplm_reg, pplm,