feature_mask      148 arch/arm64/kernel/alternative.c 				 unsigned long *feature_mask)
feature_mask      158 arch/arm64/kernel/alternative.c 		if (!test_bit(alt->cpufeature, feature_mask))
feature_mask      201 arch/arm64/kernel/alternative.c 			  feature_mask, ARM64_NCAPS);
feature_mask      194 arch/ia64/include/asm/sal.h 	u8 feature_mask;
feature_mask      153 arch/ia64/kernel/sal.c 	sal_platform_features = pf->feature_mask;
feature_mask      491 arch/x86/mm/mem_encrypt_identity.c 	unsigned long feature_mask;
feature_mask      513 arch/x86/mm/mem_encrypt_identity.c 	feature_mask = (ecx & BIT(31)) ? AMD_SEV_BIT : AMD_SME_BIT;
feature_mask      526 arch/x86/mm/mem_encrypt_identity.c 	if (!(eax & feature_mask))
feature_mask      532 arch/x86/mm/mem_encrypt_identity.c 	if (feature_mask == AMD_SME_BIT) {
feature_mask       56 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	hwmgr->feature_mask = adev->pm.pp_feature;
feature_mask       64 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	uint32_t feature_mask[2] = { 0 };
feature_mask       70 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
feature_mask       75 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 			feature_mask[1], feature_mask[0]);
feature_mask      101 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	uint32_t feature_mask[2] = { 0 };
feature_mask      106 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
feature_mask      110 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	feature_enables = ((uint64_t)feature_mask[1] << 32 | (uint64_t)feature_mask[0]);
feature_mask      572 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c int smu_feature_update_enable_state(struct smu_context *smu, uint64_t feature_mask, bool enabled)
feature_mask      580 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	feature_low = (feature_mask >> 0 ) & 0xffffffff;
feature_mask      581 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	feature_high = (feature_mask >> 32) & 0xffffffff;
feature_mask      636 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	uint64_t feature_mask = 0;
feature_mask      645 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	feature_mask = 1ULL << feature_id;
feature_mask      648 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	ret = smu_feature_update_enable_state(smu, feature_mask, enable);
feature_mask      342 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 				  uint32_t *feature_mask, uint32_t num)
feature_mask      348 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 	memset(feature_mask, 0xFF, sizeof(uint32_t) * num);
feature_mask      695 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 				     uint32_t feature_mask)
feature_mask      704 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 	    (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
feature_mask      719 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 	    (feature_mask & FEATURE_DPM_UCLK_MASK)) {
feature_mask      734 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 	    (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
feature_mask     1894 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 	uint32_t feature_mask[2];
feature_mask     1896 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 	ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
feature_mask     1897 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 	feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
feature_mask     1898 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 			   ((uint64_t)feature_mask[1] << 32));
feature_mask      101 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 		hwmgr->feature_mask &= ~(PP_VBI_TIME_SUPPORT_MASK |
feature_mask      111 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 		hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
feature_mask      115 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 		hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
feature_mask      120 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 			hwmgr->feature_mask &= ~ (PP_VBI_TIME_SUPPORT_MASK |
feature_mask      128 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 			hwmgr->feature_mask &= ~PP_VBI_TIME_SUPPORT_MASK;
feature_mask      133 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 			hwmgr->feature_mask &= ~ (PP_VBI_TIME_SUPPORT_MASK |
feature_mask      141 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 			hwmgr->feature_mask &= ~(PP_UVD_HANDSHAKE_MASK);
feature_mask      146 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 			hwmgr->feature_mask &= ~(PP_UVD_HANDSHAKE_MASK);
feature_mask      156 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 			hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
feature_mask      165 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 			hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
feature_mask      431 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	if (hwmgr->feature_mask & PP_SCLK_DEEP_SLEEP_MASK)
feature_mask      438 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	if (hwmgr->feature_mask & PP_POWER_CONTAINMENT_MASK) {
feature_mask      450 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	if (hwmgr->feature_mask & PP_OVERDRIVE_MASK)
feature_mask      170 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c 	if (!(hwmgr->feature_mask & PP_ENABLE_GFX_CG_THRU_SMU))
feature_mask      187 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	if (hwmgr->feature_mask & PP_SMC_VOLTAGE_CONTROL_MASK)
feature_mask     1098 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		if (!(hwmgr->feature_mask & PP_UVD_HANDSHAKE_MASK))
feature_mask     1570 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	data->mclk_dpm_key_disabled = hwmgr->feature_mask & PP_MCLK_DPM_MASK ? false : true;
feature_mask     1571 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	data->sclk_dpm_key_disabled = hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true;
feature_mask     1572 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	data->pcie_dpm_key_disabled = hwmgr->feature_mask & PP_PCIE_DPM_MASK ? false : true;
feature_mask     1580 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	data->ulv_supported = hwmgr->feature_mask & PP_ULV_MASK ? true : false;
feature_mask     1664 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	if ((hwmgr->pp_table_version != PP_TABLE_V0) && (hwmgr->feature_mask & PP_CLOCK_STRETCH_MASK)
feature_mask     2227 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		if (hwmgr->feature_mask & PP_OD_FUZZY_FAN_CONTROL_MASK)
feature_mask     3950 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	if (hwmgr->feature_mask & PP_VBI_TIME_SUPPORT_MASK) {
feature_mask      118 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true;
feature_mask      120 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			hwmgr->feature_mask & PP_SOCCLK_DPM_MASK ? false : true;
feature_mask      122 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			hwmgr->feature_mask & PP_MCLK_DPM_MASK ? false : true;
feature_mask      124 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			hwmgr->feature_mask & PP_PCIE_DPM_MASK ? false : true;
feature_mask      127 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			hwmgr->feature_mask & PP_DCEFCLK_DPM_MASK ? false : true;
feature_mask      129 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	if (hwmgr->feature_mask & PP_POWER_CONTAINMENT_MASK) {
feature_mask      136 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			hwmgr->feature_mask & PP_CLOCK_STRETCH_MASK ? true : false;
feature_mask      139 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			hwmgr->feature_mask & PP_ULV_MASK ? true : false;
feature_mask      142 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			hwmgr->feature_mask & PP_SCLK_DEEP_SLEEP_MASK ? true : false;
feature_mask      151 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		hwmgr->feature_mask & PP_AVFS_MASK ? true : false;
feature_mask     2829 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	uint32_t i, feature_mask = 0;
feature_mask     2843 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 					feature_mask |= data->smu_features[i].
feature_mask     2851 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	vega10_enable_smc_features(hwmgr, false, feature_mask);
feature_mask     2866 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	uint32_t i, feature_mask = 0;
feature_mask     2872 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 					feature_mask |= data->smu_features[i].
feature_mask     2881 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			true, feature_mask)) {
feature_mask     2884 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 					feature_mask)
feature_mask      437 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	if (hwmgr->feature_mask & PP_GFXOFF_MASK)
feature_mask      100 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	if (!(hwmgr->feature_mask & PP_PCIE_DPM_MASK))
feature_mask      103 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	if (!(hwmgr->feature_mask & PP_SCLK_DPM_MASK))
feature_mask      106 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	if (!(hwmgr->feature_mask & PP_SOCCLK_DPM_MASK))
feature_mask      109 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	if (!(hwmgr->feature_mask & PP_MCLK_DPM_MASK))
feature_mask      112 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	if (!(hwmgr->feature_mask & PP_DCEFCLK_DPM_MASK))
feature_mask      115 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	if (!(hwmgr->feature_mask & PP_ULV_MASK))
feature_mask      118 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	if (!(hwmgr->feature_mask & PP_SCLK_DEEP_SLEEP_MASK))
feature_mask     1793 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static int vega20_upload_dpm_min_level(struct pp_hwmgr *hwmgr, uint32_t feature_mask)
feature_mask     1801 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	   (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
feature_mask     1811 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	   (feature_mask & FEATURE_DPM_UCLK_MASK)) {
feature_mask     1821 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	   (feature_mask & FEATURE_DPM_UVD_MASK)) {
feature_mask     1840 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	   (feature_mask & FEATURE_DPM_VCE_MASK)) {
feature_mask     1851 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	   (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
feature_mask     1862 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	   (feature_mask & FEATURE_DPM_FCLK_MASK)) {
feature_mask     1873 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	   (feature_mask & FEATURE_DPM_DCEFCLK_MASK)) {
feature_mask     1886 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static int vega20_upload_dpm_max_level(struct pp_hwmgr *hwmgr, uint32_t feature_mask)
feature_mask     1894 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	   (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
feature_mask     1905 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	   (feature_mask & FEATURE_DPM_UCLK_MASK)) {
feature_mask     1916 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	   (feature_mask & FEATURE_DPM_UVD_MASK)) {
feature_mask     1934 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	   (feature_mask & FEATURE_DPM_VCE_MASK)) {
feature_mask     1945 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	   (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
feature_mask     1956 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	   (feature_mask & FEATURE_DPM_FCLK_MASK)) {
feature_mask      403 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*get_allowed_feature_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
feature_mask      497 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*get_enabled_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
feature_mask      703 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_get_allowed_feature_mask(smu, feature_mask, num) \
feature_mask      704 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->ppt_funcs? ((smu)->ppt_funcs->get_allowed_feature_mask? (smu)->ppt_funcs->get_allowed_feature_mask((smu), (feature_mask), (num)) : 0) : 0)
feature_mask      832 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h int smu_feature_update_enable_state(struct smu_context *smu, uint64_t feature_mask, bool enabled);
feature_mask      784 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	uint32_t feature_mask;
feature_mask      320 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 				  uint32_t *feature_mask, uint32_t num)
feature_mask      327 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	memset(feature_mask, 0, sizeof(uint32_t) * num);
feature_mask      329 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
feature_mask      355 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
feature_mask      360 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
feature_mask      362 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 		*(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_FW_DSTATE_BIT);
feature_mask      366 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
feature_mask      369 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
feature_mask      372 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT)
feature_mask      380 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 			*(uint64_t *)feature_mask &=
feature_mask      384 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 			*(uint64_t *)feature_mask &=
feature_mask      992 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	uint32_t feature_mask[2];
feature_mask      994 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
feature_mask      995 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 	feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
feature_mask      996 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 			   ((uint64_t)feature_mask[1] << 32));
feature_mask      850 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	uint32_t feature_mask[2];
feature_mask      856 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	bitmap_copy((unsigned long *)feature_mask, feature->allowed, 64);
feature_mask      859 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 					  feature_mask[1]);
feature_mask      864 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 					  feature_mask[0]);
feature_mask      874 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 				      uint32_t *feature_mask, uint32_t num)
feature_mask      879 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	if (!feature_mask || num < 2)
feature_mask      896 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	feature_mask[0] = feature_mask_low;
feature_mask      897 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	feature_mask[1] = feature_mask_high;
feature_mask      906 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	uint32_t feature_mask[2];
feature_mask      916 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
feature_mask      920 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
feature_mask      922 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 	bitmap_copy(feature->supported, (unsigned long *)&feature_mask,
feature_mask      585 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	    (hwmgr->feature_mask & PP_AVFS_MASK))
feature_mask       98 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c 			       bool enable, uint32_t feature_mask)
feature_mask      104 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c 			msg, feature_mask);
feature_mask       46 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.h 			       bool enable, uint32_t feature_mask);
feature_mask      118 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c 		bool enable, uint64_t feature_mask)
feature_mask      122 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c 	smu_features_low = (uint32_t)((feature_mask & SMU_FEATURES_LOW_MASK) >> SMU_FEATURES_LOW_SHIFT);
feature_mask      123 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c 	smu_features_high = (uint32_t)((feature_mask & SMU_FEATURES_HIGH_MASK) >> SMU_FEATURES_HIGH_SHIFT);
feature_mask       52 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.h 		bool enable, uint64_t feature_mask);
feature_mask      302 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 		bool enable, uint64_t feature_mask)
feature_mask      307 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 	smu_features_low = (uint32_t)((feature_mask & SMU_FEATURES_LOW_MASK) >> SMU_FEATURES_LOW_SHIFT);
feature_mask      308 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 	smu_features_high = (uint32_t)((feature_mask & SMU_FEATURES_HIGH_MASK) >> SMU_FEATURES_HIGH_SHIFT);
feature_mask       51 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.h 		bool enable, uint64_t feature_mask);
feature_mask      591 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 				  uint32_t *feature_mask, uint32_t num)
feature_mask      596 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	memset(feature_mask, 0, sizeof(uint32_t) * num);
feature_mask      598 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
feature_mask     1184 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 				   uint32_t feature_mask)
feature_mask     1194 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	    (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
feature_mask     1209 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	    (feature_mask & FEATURE_DPM_UCLK_MASK)) {
feature_mask     1224 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	    (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
feature_mask     1239 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	    (feature_mask & FEATURE_DPM_FCLK_MASK)) {
feature_mask     1254 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	    (feature_mask & FEATURE_DPM_DCEFCLK_MASK)) {
feature_mask     2867 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	uint32_t feature_mask[2];
feature_mask     2869 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
feature_mask     2870 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
feature_mask     2871 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 			   ((uint64_t)feature_mask[1] << 32));
feature_mask      358 drivers/infiniband/hw/efa/efa_com_cmd.c 	u32 feature_mask = 1 << feature_id;
feature_mask      362 drivers/infiniband/hw/efa/efa_com_cmd.c 	    !(edev->supported_features & feature_mask))
feature_mask      256 drivers/infiniband/hw/qib/qib_iba7322.c #define kr_fmask KREG_IDX(feature_mask)
feature_mask       66 drivers/mfd/kempld-core.c 		pld->feature_mask = kempld_read16(pld, KEMPLD_FEATURE);
feature_mask       68 drivers/mfd/kempld-core.c 		pld->feature_mask = 0;
feature_mask      104 drivers/mfd/kempld-core.c 	if (pld->feature_mask & KEMPLD_FEATURE_BIT_I2C)
feature_mask      107 drivers/mfd/kempld-core.c 	if (pld->feature_mask & KEMPLD_FEATURE_BIT_WATCHDOG)
feature_mask      110 drivers/mfd/kempld-core.c 	if (pld->feature_mask & KEMPLD_FEATURE_BIT_GPIO)
feature_mask      113 drivers/mfd/kempld-core.c 	if (pld->feature_mask & KEMPLD_FEATURE_MASK_UART)
feature_mask      972 drivers/net/ethernet/amazon/ena/ena_com.c 	u32 feature_mask = 1 << feature_id;
feature_mask      976 drivers/net/ethernet/amazon/ena/ena_com.c 	    !(ena_dev->supported_features & feature_mask))
feature_mask      630 drivers/net/ethernet/qlogic/qed/qed_vf.c 			   u16 feature_mask, u8 tunn_mode,
feature_mask      633 drivers/net/ethernet/qlogic/qed/qed_vf.c 	if (feature_mask & BIT(val)) {
feature_mask      929 drivers/net/tap.c 	netdev_features_t feature_mask = 0;
feature_mask      938 drivers/net/tap.c 		feature_mask = NETIF_F_HW_CSUM;
feature_mask      942 drivers/net/tap.c 				feature_mask |= NETIF_F_TSO_ECN;
feature_mask      944 drivers/net/tap.c 				feature_mask |= NETIF_F_TSO;
feature_mask      946 drivers/net/tap.c 				feature_mask |= NETIF_F_TSO6;
feature_mask      958 drivers/net/tap.c 	if (feature_mask & (NETIF_F_TSO | NETIF_F_TSO6))
feature_mask      966 drivers/net/tap.c 	tap->tap_features = feature_mask;
feature_mask     6661 drivers/net/wireless/ath/ath10k/wmi.c 	cmd->resource_config.feature_mask = __cpu_to_le32(features);
feature_mask     2731 drivers/net/wireless/ath/ath10k/wmi.h 	__le32 feature_mask;
feature_mask      403 drivers/watchdog/kempld_wdt.c 			if (pld->feature_mask & KEMPLD_FEATURE_BIT_NMI) {
feature_mask       91 include/linux/mfd/kempld.h 	u32			feature_mask;
feature_mask       71 sound/soc/intel/skylake/skl-sst-utils.c 	u32 feature_mask;