fbdiv 1183 arch/arm/common/sa1111.c unsigned int skcdr, fbdiv, ipdiv, opdiv; fbdiv 1187 arch/arm/common/sa1111.c fbdiv = (skcdr & 0x007f) + 2; fbdiv 1191 arch/arm/common/sa1111.c return 3686400 * fbdiv / (ipdiv * opdiv); fbdiv 120 arch/mips/ralink/mt7621.c int fbdiv = 0; fbdiv 137 arch/mips/ralink/mt7621.c fbdiv = ((rt_sysc_r32(0x648) >> 4) & 0x7F) + 1; fbdiv 142 arch/mips/ralink/mt7621.c cpu_clk = 25 * fbdiv * 1000 * 1000; fbdiv 145 arch/mips/ralink/mt7621.c cpu_clk = 40 * fbdiv * 1000 * 1000; fbdiv 148 arch/mips/ralink/mt7621.c cpu_clk = 20 * fbdiv * 1000 * 1000; fbdiv 227 drivers/clk/analogbits/wrpll-cln28hpc.c u8 fbdiv, divq, best_r, r; fbdiv 263 drivers/clk/analogbits/wrpll-cln28hpc.c fbdiv = __wrpll_calc_fbdiv(c); fbdiv 275 drivers/clk/analogbits/wrpll-cln28hpc.c f >>= (fbdiv - 1); fbdiv 278 drivers/clk/analogbits/wrpll-cln28hpc.c vco_pre = fbdiv * post_divr_freq; fbdiv 333 drivers/clk/analogbits/wrpll-cln28hpc.c u8 fbdiv; fbdiv 341 drivers/clk/analogbits/wrpll-cln28hpc.c fbdiv = __wrpll_calc_fbdiv(c); fbdiv 342 drivers/clk/analogbits/wrpll-cln28hpc.c n = parent_rate * fbdiv * (c->divf + 1); fbdiv 30 drivers/clk/axs10x/i2s_pll_clock.c unsigned int fbdiv; fbdiv 105 drivers/clk/axs10x/i2s_pll_clock.c unsigned int idiv, fbdiv, odiv; fbdiv 108 drivers/clk/axs10x/i2s_pll_clock.c fbdiv = i2s_pll_get_value(i2s_pll_read(clk, PLL_FBDIV_REG)); fbdiv 111 drivers/clk/axs10x/i2s_pll_clock.c return ((parent_rate / idiv) * fbdiv) / odiv; fbdiv 148 drivers/clk/axs10x/i2s_pll_clock.c i2s_pll_write(clk, PLL_FBDIV_REG, pll_cfg[i].fbdiv); fbdiv 73 drivers/clk/axs10x/pll_clock.c u32 fbdiv; fbdiv 143 drivers/clk/axs10x/pll_clock.c u32 idiv, fbdiv, odiv; fbdiv 147 drivers/clk/axs10x/pll_clock.c fbdiv = axs10x_div_get_value(axs10x_pll_read(clk, PLL_REG_FBDIV)); fbdiv 150 drivers/clk/axs10x/pll_clock.c rate = (u64)parent_rate * fbdiv; fbdiv 189 drivers/clk/axs10x/pll_clock.c axs10x_encode_div(pll_cfg[i].fbdiv, 0)); fbdiv 159 drivers/clk/berlin/berlin2-avpll.c u32 reg, refdiv, fbdiv; fbdiv 166 drivers/clk/berlin/berlin2-avpll.c fbdiv = (reg & VCO_FBDIV_MASK) >> VCO_FBDIV_SHIFT; fbdiv 167 drivers/clk/berlin/berlin2-avpll.c freq *= fbdiv; fbdiv 46 drivers/clk/berlin/berlin2-pll.c u32 val, fbdiv, rfdiv, vcodivsel, vcodiv; fbdiv 50 drivers/clk/berlin/berlin2-pll.c fbdiv = (val >> map->fbdiv_shift) & FBDIV_MASK; fbdiv 66 drivers/clk/berlin/berlin2-pll.c rate *= fbdiv * map->mult; fbdiv 52 drivers/clk/clk-axm5516.c unsigned long rate, fbdiv, refdiv, postdiv; fbdiv 57 drivers/clk/clk-axm5516.c fbdiv = ((control >> 4) & 0xfff) + 3; fbdiv 59 drivers/clk/clk-axm5516.c rate = (parent_rate / (refdiv * postdiv)) * fbdiv; fbdiv 53 drivers/clk/clk-hsdk-pll.c u32 fbdiv; fbdiv 139 drivers/clk/clk-hsdk-pll.c val |= cfg->fbdiv << CGU_PLL_CTRL_FBDIV_SHIFT; fbdiv 168 drivers/clk/clk-hsdk-pll.c u32 idiv, fbdiv, odiv; fbdiv 186 drivers/clk/clk-hsdk-pll.c fbdiv = 2 * (1 + ((val & CGU_PLL_CTRL_FBDIV_MASK) >> CGU_PLL_CTRL_FBDIV_SHIFT)); fbdiv 190 drivers/clk/clk-hsdk-pll.c rate = (u64)parent_rate * fbdiv; fbdiv 211 drivers/clk/pistachio/clk-pll.c vco *= (params->fbdiv << 24) + params->frac; fbdiv 230 drivers/clk/pistachio/clk-pll.c (params->fbdiv << PLL_CTRL1_FBDIV_SHIFT); fbdiv 273 drivers/clk/pistachio/clk-pll.c u64 val, prediv, fbdiv, frac, postdiv1, postdiv2, rate; fbdiv 277 drivers/clk/pistachio/clk-pll.c fbdiv = (val >> PLL_CTRL1_FBDIV_SHIFT) & PLL_CTRL1_FBDIV_MASK; fbdiv 289 drivers/clk/pistachio/clk-pll.c rate *= (fbdiv << 24) + frac; fbdiv 291 drivers/clk/pistachio/clk-pll.c rate *= (fbdiv << 24); fbdiv 366 drivers/clk/pistachio/clk-pll.c vco = div_u64(params->fref * params->fbdiv, params->refdiv); fbdiv 398 drivers/clk/pistachio/clk-pll.c (params->fbdiv << PLL_CTRL1_FBDIV_SHIFT) | fbdiv 413 drivers/clk/pistachio/clk-pll.c u32 val, prediv, fbdiv, postdiv1, postdiv2; fbdiv 418 drivers/clk/pistachio/clk-pll.c fbdiv = (val >> PLL_CTRL1_FBDIV_SHIFT) & PLL_CTRL1_FBDIV_MASK; fbdiv 424 drivers/clk/pistachio/clk-pll.c rate *= fbdiv; fbdiv 98 drivers/clk/pistachio/clk.h unsigned long long fbdiv; fbdiv 134 drivers/clk/rockchip/clk-pll.c rate->fbdiv = ((pllcon >> RK3036_PLLCON0_FBDIV_SHIFT) fbdiv 161 drivers/clk/rockchip/clk-pll.c rate64 *= cur.fbdiv; fbdiv 190 drivers/clk/rockchip/clk-pll.c __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv, fbdiv 203 drivers/clk/rockchip/clk-pll.c writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3036_PLLCON0_FBDIV_MASK, fbdiv 307 drivers/clk/rockchip/clk-pll.c cur.fbdiv, cur.postdiv1, cur.refdiv, cur.postdiv2, fbdiv 310 drivers/clk/rockchip/clk-pll.c rate->fbdiv, rate->postdiv1, rate->refdiv, rate->postdiv2, fbdiv 313 drivers/clk/rockchip/clk-pll.c if (rate->fbdiv != cur.fbdiv || rate->postdiv1 != cur.postdiv1 || fbdiv 609 drivers/clk/rockchip/clk-pll.c rate->fbdiv = ((pllcon >> RK3399_PLLCON0_FBDIV_SHIFT) fbdiv 638 drivers/clk/rockchip/clk-pll.c rate64 *= cur.fbdiv; fbdiv 667 drivers/clk/rockchip/clk-pll.c __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv, fbdiv 680 drivers/clk/rockchip/clk-pll.c writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3399_PLLCON0_FBDIV_MASK, fbdiv 786 drivers/clk/rockchip/clk-pll.c cur.fbdiv, cur.postdiv1, cur.refdiv, cur.postdiv2, fbdiv 789 drivers/clk/rockchip/clk-pll.c rate->fbdiv, rate->postdiv1, rate->refdiv, rate->postdiv2, fbdiv 792 drivers/clk/rockchip/clk-pll.c if (rate->fbdiv != cur.fbdiv || rate->postdiv1 != cur.postdiv1 || fbdiv 202 drivers/clk/rockchip/clk.h .fbdiv = _fbdiv, \ fbdiv 251 drivers/clk/rockchip/clk.h unsigned int fbdiv; fbdiv 54 drivers/clk/zynq/pll.c u32 fbdiv; fbdiv 56 drivers/clk/zynq/pll.c fbdiv = DIV_ROUND_CLOSEST(rate, *prate); fbdiv 57 drivers/clk/zynq/pll.c if (fbdiv < PLL_FBDIV_MIN) fbdiv 58 drivers/clk/zynq/pll.c fbdiv = PLL_FBDIV_MIN; fbdiv 59 drivers/clk/zynq/pll.c else if (fbdiv > PLL_FBDIV_MAX) fbdiv 60 drivers/clk/zynq/pll.c fbdiv = PLL_FBDIV_MAX; fbdiv 62 drivers/clk/zynq/pll.c return *prate * fbdiv; fbdiv 75 drivers/clk/zynq/pll.c u32 fbdiv; fbdiv 81 drivers/clk/zynq/pll.c fbdiv = (readl(clk->pll_ctrl) & PLLCTRL_FBDIV_MASK) >> fbdiv 84 drivers/clk/zynq/pll.c return parent_rate * fbdiv; fbdiv 100 drivers/clk/zynqmp/pll.c u32 fbdiv; fbdiv 110 drivers/clk/zynqmp/pll.c fbdiv = rate / PS_PLL_VCO_MAX; fbdiv 111 drivers/clk/zynqmp/pll.c rate = rate / (fbdiv + 1); fbdiv 114 drivers/clk/zynqmp/pll.c fbdiv = DIV_ROUND_UP(PS_PLL_VCO_MIN, rate); fbdiv 115 drivers/clk/zynqmp/pll.c rate = rate * fbdiv; fbdiv 120 drivers/clk/zynqmp/pll.c fbdiv = DIV_ROUND_CLOSEST(rate, *prate); fbdiv 121 drivers/clk/zynqmp/pll.c fbdiv = clamp_t(u32, fbdiv, PLL_FBDIV_MIN, PLL_FBDIV_MAX); fbdiv 122 drivers/clk/zynqmp/pll.c return *prate * fbdiv; fbdiv 138 drivers/clk/zynqmp/pll.c u32 fbdiv, data; fbdiv 144 drivers/clk/zynqmp/pll.c ret = eemi_ops->clock_getdivider(clk_id, &fbdiv); fbdiv 149 drivers/clk/zynqmp/pll.c rate = parent_rate * fbdiv; fbdiv 177 drivers/clk/zynqmp/pll.c u32 fbdiv; fbdiv 200 drivers/clk/zynqmp/pll.c fbdiv = DIV_ROUND_CLOSEST(rate, parent_rate); fbdiv 201 drivers/clk/zynqmp/pll.c fbdiv = clamp_t(u32, fbdiv, PLL_FBDIV_MIN, PLL_FBDIV_MAX); fbdiv 202 drivers/clk/zynqmp/pll.c ret = eemi_ops->clock_setdivider(clk_id, fbdiv); fbdiv 207 drivers/clk/zynqmp/pll.c return parent_rate * fbdiv; fbdiv 5260 drivers/gpu/drm/amd/amdgpu/si_dpm.c u32 fbdiv; fbdiv 5272 drivers/gpu/drm/amd/amdgpu/si_dpm.c fbdiv = (u32) tmp; fbdiv 5282 drivers/gpu/drm/amd/amdgpu/si_dpm.c spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); fbdiv 5292 drivers/gpu/drm/amd/amdgpu/si_dpm.c u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); fbdiv 307 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t fbdiv; fbdiv 322 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF; fbdiv 332 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c SPLL_FB_DIV, fbdiv); fbdiv 348 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c fbdiv / (clk_s * 10000); fbdiv 869 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c uint32_t fbdiv; fbdiv 884 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF; fbdiv 894 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c SPLL_FB_DIV, fbdiv); fbdiv 917 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c fbdiv / (clk_s * 10000); fbdiv 807 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t fbdiv; fbdiv 822 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF; fbdiv 832 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c CG_SPLL_FUNC_CNTL_3, SPLL_FB_DIV, fbdiv); fbdiv 852 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t clkV = 4 * ss_info.speed_spectrum_percentage * fbdiv / (clkS * 10000); fbdiv 550 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t fbdiv; fbdiv 565 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF; fbdiv 575 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c CG_SPLL_FUNC_CNTL_3, SPLL_FB_DIV, fbdiv); fbdiv 595 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t clkV = 4 * ss_info.speed_spectrum_percentage * fbdiv / (clkS * 10000); fbdiv 3171 drivers/gpu/drm/radeon/ci_dpm.c u32 fbdiv; fbdiv 3181 drivers/gpu/drm/radeon/ci_dpm.c fbdiv = dividers.fb_div & 0x3FFFFFF; fbdiv 3184 drivers/gpu/drm/radeon/ci_dpm.c spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); fbdiv 3194 drivers/gpu/drm/radeon/ci_dpm.c u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); fbdiv 2014 drivers/gpu/drm/radeon/ni_dpm.c u32 fbdiv; fbdiv 2027 drivers/gpu/drm/radeon/ni_dpm.c fbdiv = (u32) tmp; fbdiv 2037 drivers/gpu/drm/radeon/ni_dpm.c spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); fbdiv 2047 drivers/gpu/drm/radeon/ni_dpm.c u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); fbdiv 213 drivers/gpu/drm/radeon/rs780_dpm.c u32 fbdiv = (RREG32(CG_SPLL_FUNC_CNTL) & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; fbdiv 215 drivers/gpu/drm/radeon/rs780_dpm.c WREG32_P(FVTHROT_FBDIV_REG1, STARTING_FEEDBACK_DIV(fbdiv), fbdiv 218 drivers/gpu/drm/radeon/rs780_dpm.c WREG32_P(FVTHROT_FBDIV_REG2, FORCED_FEEDBACK_DIV(fbdiv), fbdiv 53 drivers/gpu/drm/radeon/rv730_dpm.c u32 fbdiv; fbdiv 71 drivers/gpu/drm/radeon/rv730_dpm.c fbdiv = (u32) tmp; fbdiv 87 drivers/gpu/drm/radeon/rv730_dpm.c spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); fbdiv 97 drivers/gpu/drm/radeon/rv730_dpm.c u32 clk_v = ss.percentage * fbdiv / (clk_s * 10000); fbdiv 133 drivers/gpu/drm/radeon/rv740_dpm.c u32 fbdiv; fbdiv 145 drivers/gpu/drm/radeon/rv740_dpm.c fbdiv = (u32) tmp; fbdiv 155 drivers/gpu/drm/radeon/rv740_dpm.c spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); fbdiv 165 drivers/gpu/drm/radeon/rv740_dpm.c u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); fbdiv 502 drivers/gpu/drm/radeon/rv770_dpm.c u32 fbdiv; fbdiv 519 drivers/gpu/drm/radeon/rv770_dpm.c fbdiv = (u32) tmp; fbdiv 534 drivers/gpu/drm/radeon/rv770_dpm.c spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); fbdiv 544 drivers/gpu/drm/radeon/rv770_dpm.c u32 clk_v = ss.percentage * fbdiv / (clk_s * 10000); fbdiv 4798 drivers/gpu/drm/radeon/si_dpm.c u32 fbdiv; fbdiv 4810 drivers/gpu/drm/radeon/si_dpm.c fbdiv = (u32) tmp; fbdiv 4820 drivers/gpu/drm/radeon/si_dpm.c spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); fbdiv 4830 drivers/gpu/drm/radeon/si_dpm.c u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); fbdiv 254 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c u16 fbdiv; fbdiv 269 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c u16 fbdiv; fbdiv 642 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c RK3228_PRE_PLL_FB_DIV_8(cfg->fbdiv) | fbdiv 645 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c inno_write(inno, 0xe3, RK3228_PRE_PLL_FB_DIV_7_0(cfg->fbdiv)); fbdiv 800 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c inno_write(inno, 0xa2, RK3328_PRE_PLL_FB_DIV_11_8(cfg->fbdiv) | val); fbdiv 801 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c inno_write(inno, 0xa3, RK3328_PRE_PLL_FB_DIV_7_0(cfg->fbdiv)); fbdiv 914 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c RK3228_POST_PLL_FB_DIV_8(cfg->fbdiv)); fbdiv 915 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c inno_write(inno, 0xea, RK3228_POST_PLL_FB_DIV_7_0(cfg->fbdiv)); fbdiv 1022 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c inno_write(inno, 0xac, RK3328_POST_PLL_FB_DIV_7_0(cfg->fbdiv)); fbdiv 1025 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c inno_write(inno, 0xab, RK3328_POST_PLL_FB_DIV_8(cfg->fbdiv) | fbdiv 1031 drivers/phy/rockchip/phy-rockchip-inno-hdmi.c inno_write(inno, 0xab, RK3328_POST_PLL_FB_DIV_8(cfg->fbdiv) | fbdiv 124 drivers/soc/xilinx/xlnx_vcu.c u32 fbdiv; fbdiv 346 drivers/soc/xilinx/xlnx_vcu.c fvco = cfg->fbdiv * refclk; fbdiv 384 drivers/soc/xilinx/xlnx_vcu.c vcu_pll_ctrl |= (found->fbdiv & VCU_PLL_CTRL_FBDIV_MASK) << fbdiv 4307 sound/soc/codecs/madera.c int refdiv, fref, fout, lockdet_thr, fbdiv, hp, fast_clk, fllgcd; fbdiv 4331 sound/soc/codecs/madera.c fbdiv = 256; fbdiv 4333 sound/soc/codecs/madera.c fbdiv = 4; fbdiv 4337 sound/soc/codecs/madera.c fbdiv = 1; fbdiv 4341 sound/soc/codecs/madera.c fbdiv = 1; fbdiv 4366 sound/soc/codecs/madera.c while (ratio / fbdiv < min_n) { fbdiv 4367 sound/soc/codecs/madera.c fbdiv /= 2; fbdiv 4368 sound/soc/codecs/madera.c if (fbdiv < 1) { fbdiv 4369 sound/soc/codecs/madera.c madera_fll_err(fll, "FBDIV (%d) must be >= 1\n", fbdiv); fbdiv 4373 sound/soc/codecs/madera.c while (frac && (ratio / fbdiv > max_n)) { fbdiv 4374 sound/soc/codecs/madera.c fbdiv *= 2; fbdiv 4375 sound/soc/codecs/madera.c if (fbdiv >= 1024) { fbdiv 4376 sound/soc/codecs/madera.c madera_fll_err(fll, "FBDIV (%u) >= 1024\n", fbdiv); fbdiv 4382 sound/soc/codecs/madera.c lockdet_thr, hp, fbdiv); fbdiv 4385 sound/soc/codecs/madera.c fllgcd = gcd(fout, fbdiv * fref); fbdiv 4387 sound/soc/codecs/madera.c lambda = (fref * fbdiv) / fllgcd; fbdiv 4401 sound/soc/codecs/madera.c if (fbdiv < 1 || (frac && fbdiv >= 1024) || (!frac && fbdiv >= 256)) { fbdiv 4403 sound/soc/codecs/madera.c frac ? "fractional" : "integer", fbdiv); fbdiv 4422 sound/soc/codecs/madera.c fbdiv << MADERA_FLL1_FB_DIV_SHIFT);