fbc_ctl 10934 drivers/gpu/drm/i915/display/intel_display.c u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0; fbc_ctl 10942 drivers/gpu/drm/i915/display/intel_display.c fbc_ctl = CUR_FBC_CTL_EN | (plane_state->base.crtc_h - 1); fbc_ctl 10974 drivers/gpu/drm/i915/display/intel_display.c plane->cursor.size != fbc_ctl || fbc_ctl 10977 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE_FW(CUR_FBC_CTL(pipe), fbc_ctl); fbc_ctl 10983 drivers/gpu/drm/i915/display/intel_display.c plane->cursor.size = fbc_ctl; fbc_ctl 102 drivers/gpu/drm/i915/display/intel_fbc.c u32 fbc_ctl; fbc_ctl 105 drivers/gpu/drm/i915/display/intel_fbc.c fbc_ctl = I915_READ(FBC_CONTROL); fbc_ctl 106 drivers/gpu/drm/i915/display/intel_fbc.c if ((fbc_ctl & FBC_CTL_EN) == 0) fbc_ctl 109 drivers/gpu/drm/i915/display/intel_fbc.c fbc_ctl &= ~FBC_CTL_EN; fbc_ctl 110 drivers/gpu/drm/i915/display/intel_fbc.c I915_WRITE(FBC_CONTROL, fbc_ctl); fbc_ctl 125 drivers/gpu/drm/i915/display/intel_fbc.c u32 fbc_ctl; fbc_ctl 153 drivers/gpu/drm/i915/display/intel_fbc.c fbc_ctl = I915_READ(FBC_CONTROL); fbc_ctl 154 drivers/gpu/drm/i915/display/intel_fbc.c fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT; fbc_ctl 155 drivers/gpu/drm/i915/display/intel_fbc.c fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC; fbc_ctl 157 drivers/gpu/drm/i915/display/intel_fbc.c fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */ fbc_ctl 158 drivers/gpu/drm/i915/display/intel_fbc.c fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT; fbc_ctl 159 drivers/gpu/drm/i915/display/intel_fbc.c fbc_ctl |= params->vma->fence->id; fbc_ctl 160 drivers/gpu/drm/i915/display/intel_fbc.c I915_WRITE(FBC_CONTROL, fbc_ctl);