fb_div 41 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h u32 fb_div; fb_div 66 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h u32 fb_div; fb_div 85 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c unsigned *fb_div, unsigned *ref_div) fb_div 92 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den); fb_div 95 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c if (*fb_div > fb_div_max) { fb_div 96 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c *ref_div = DIV_ROUND_CLOSEST(*ref_div * fb_div_max, *fb_div); fb_div 97 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c *fb_div = fb_div_max; fb_div 125 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c unsigned fb_div_min, fb_div_max, fb_div; fb_div 202 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c ref_div_max, &fb_div, &ref_div); fb_div 203 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c diff = abs(target_clock - (pll->reference_freq * fb_div) / fb_div 217 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c &fb_div, &ref_div); fb_div 221 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c amdgpu_pll_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min); fb_div 224 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) { fb_div 225 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 60); fb_div 226 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c if (fb_div < fb_div_min) { fb_div 227 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div); fb_div 228 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c fb_div *= tmp; fb_div 235 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c *fb_div_p = fb_div / 10; fb_div 236 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c *frac_fb_div_p = fb_div % 10; fb_div 238 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c *fb_div_p = fb_div; fb_div 583 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c u32 fb_div, fb_div 610 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c args.v1.usFbDiv = cpu_to_le16(fb_div); fb_div 620 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c args.v2.usFbDiv = cpu_to_le16(fb_div); fb_div 630 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c args.v3.usFbDiv = cpu_to_le16(fb_div); fb_div 647 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c args.v5.usFbDiv = cpu_to_le16(fb_div); fb_div 677 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c args.v6.usFbDiv = cpu_to_le16(fb_div); fb_div 826 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; fb_div 855 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c &fb_div, &frac_fb_div, &ref_div, &post_div); fb_div 862 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c ref_div, fb_div, frac_fb_div, post_div, fb_div 868 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c u32 amount = (((fb_div * 10) + frac_fb_div) * fb_div 49 drivers/gpu/drm/amd/amdgpu/atombios_crtc.h u32 fb_div, fb_div 2952 drivers/gpu/drm/amd/amdgpu/si_dpm.c u32 fb_div, p_div; fb_div 2971 drivers/gpu/drm/amd/amdgpu/si_dpm.c fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; fb_div 2975 drivers/gpu/drm/amd/amdgpu/si_dpm.c fb_div &= ~0x00001FFF; fb_div 2976 drivers/gpu/drm/amd/amdgpu/si_dpm.c fb_div >>= 1; fb_div 2981 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT)) fb_div 2991 drivers/gpu/drm/amd/amdgpu/si_dpm.c tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) | fb_div 651 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c struct fixed31_32 fb_div; fb_div 671 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c fb_div = dc_fixpt_from_fraction( fb_div 673 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c fb_div = dc_fixpt_add_int(fb_div, pll_settings->feedback_divider); fb_div 679 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c fb_div, dc_fixpt_from_fraction(ss_data->percentage, fb_div 830 drivers/gpu/drm/radeon/atombios_crtc.c u32 fb_div, fb_div 857 drivers/gpu/drm/radeon/atombios_crtc.c args.v1.usFbDiv = cpu_to_le16(fb_div); fb_div 867 drivers/gpu/drm/radeon/atombios_crtc.c args.v2.usFbDiv = cpu_to_le16(fb_div); fb_div 877 drivers/gpu/drm/radeon/atombios_crtc.c args.v3.usFbDiv = cpu_to_le16(fb_div); fb_div 894 drivers/gpu/drm/radeon/atombios_crtc.c args.v5.usFbDiv = cpu_to_le16(fb_div); fb_div 923 drivers/gpu/drm/radeon/atombios_crtc.c args.v6.usFbDiv = cpu_to_le16(fb_div); fb_div 1072 drivers/gpu/drm/radeon/atombios_crtc.c u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; fb_div 1104 drivers/gpu/drm/radeon/atombios_crtc.c &fb_div, &frac_fb_div, &ref_div, &post_div); fb_div 1107 drivers/gpu/drm/radeon/atombios_crtc.c &fb_div, &frac_fb_div, &ref_div, &post_div); fb_div 1110 drivers/gpu/drm/radeon/atombios_crtc.c &fb_div, &frac_fb_div, &ref_div, &post_div); fb_div 1117 drivers/gpu/drm/radeon/atombios_crtc.c ref_div, fb_div, frac_fb_div, post_div, fb_div 1124 drivers/gpu/drm/radeon/atombios_crtc.c u32 amount = (((fb_div * 10) + frac_fb_div) * fb_div 3181 drivers/gpu/drm/radeon/ci_dpm.c fbdiv = dividers.fb_div & 0x3FFFFFF; fb_div 1195 drivers/gpu/drm/radeon/evergreen.c unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; fb_div 1214 drivers/gpu/drm/radeon/evergreen.c &fb_div, &vclk_div, &dclk_div); fb_div 1241 drivers/gpu/drm/radeon/evergreen.c WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), ~UPLL_FB_DIV_MASK); fb_div 1246 drivers/gpu/drm/radeon/evergreen.c if (fb_div < 307200) fb_div 2096 drivers/gpu/drm/radeon/ni_dpm.c u32 fb_div; fb_div 2117 drivers/gpu/drm/radeon/ni_dpm.c fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; fb_div 2121 drivers/gpu/drm/radeon/ni_dpm.c fb_div &= ~0x00001FFF; fb_div 2122 drivers/gpu/drm/radeon/ni_dpm.c fb_div >>= 1; fb_div 2140 drivers/gpu/drm/radeon/ni_dpm.c tmp = ((fb_div << SMC_NISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_NISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) | fb_div 205 drivers/gpu/drm/radeon/r600.c unsigned fb_div = 0, ref_div, vclk_div = 0, dclk_div = 0; fb_div 234 drivers/gpu/drm/radeon/r600.c &fb_div, &vclk_div, &dclk_div); fb_div 239 drivers/gpu/drm/radeon/r600.c fb_div >>= 1; fb_div 241 drivers/gpu/drm/radeon/r600.c fb_div |= 1; fb_div 257 drivers/gpu/drm/radeon/r600.c UPLL_FB_DIV(fb_div) | fb_div 2862 drivers/gpu/drm/radeon/radeon_atombios.c dividers->fb_div = args.v1.ucFbDiv; fb_div 2876 drivers/gpu/drm/radeon/radeon_atombios.c dividers->fb_div = le16_to_cpu(args.v2.usFbDiv); fb_div 2883 drivers/gpu/drm/radeon/radeon_atombios.c dividers->enable_post_div = (dividers->fb_div & 1) ? true : false; fb_div 42 drivers/gpu/drm/radeon/radeon_clocks.c uint32_t fb_div, ref_div, post_div, sclk; fb_div 44 drivers/gpu/drm/radeon/radeon_clocks.c fb_div = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV); fb_div 45 drivers/gpu/drm/radeon/radeon_clocks.c fb_div = (fb_div >> RADEON_SPLL_FB_DIV_SHIFT) & RADEON_SPLL_FB_DIV_MASK; fb_div 46 drivers/gpu/drm/radeon/radeon_clocks.c fb_div <<= 1; fb_div 47 drivers/gpu/drm/radeon/radeon_clocks.c fb_div *= spll->reference_freq; fb_div 55 drivers/gpu/drm/radeon/radeon_clocks.c sclk = fb_div / ref_div; fb_div 72 drivers/gpu/drm/radeon/radeon_clocks.c uint32_t fb_div, ref_div, post_div, mclk; fb_div 74 drivers/gpu/drm/radeon/radeon_clocks.c fb_div = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV); fb_div 75 drivers/gpu/drm/radeon/radeon_clocks.c fb_div = (fb_div >> RADEON_MPLL_FB_DIV_SHIFT) & RADEON_MPLL_FB_DIV_MASK; fb_div 76 drivers/gpu/drm/radeon/radeon_clocks.c fb_div <<= 1; fb_div 77 drivers/gpu/drm/radeon/radeon_clocks.c fb_div *= mpll->reference_freq; fb_div 85 drivers/gpu/drm/radeon/radeon_clocks.c mclk = fb_div / ref_div; fb_div 352 drivers/gpu/drm/radeon/radeon_clocks.c int *fb_div, int *post_div) fb_div 378 drivers/gpu/drm/radeon/radeon_clocks.c *fb_div = req_clock & 0xff; fb_div 393 drivers/gpu/drm/radeon/radeon_clocks.c int fb_div, post_div; fb_div 397 drivers/gpu/drm/radeon/radeon_clocks.c eng_clock = calc_eng_mem_clock(rdev, eng_clock, &fb_div, &post_div); fb_div 423 drivers/gpu/drm/radeon/radeon_clocks.c tmp |= (fb_div & RADEON_SPLL_FB_DIV_MASK) << RADEON_SPLL_FB_DIV_SHIFT; fb_div 926 drivers/gpu/drm/radeon/radeon_display.c unsigned *fb_div, unsigned *ref_div) fb_div 933 drivers/gpu/drm/radeon/radeon_display.c *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den); fb_div 936 drivers/gpu/drm/radeon/radeon_display.c if (*fb_div > fb_div_max) { fb_div 937 drivers/gpu/drm/radeon/radeon_display.c *ref_div = (*ref_div * fb_div_max)/(*fb_div); fb_div 938 drivers/gpu/drm/radeon/radeon_display.c *fb_div = fb_div_max; fb_div 966 drivers/gpu/drm/radeon/radeon_display.c unsigned fb_div_min, fb_div_max, fb_div; fb_div 1046 drivers/gpu/drm/radeon/radeon_display.c ref_div_max, &fb_div, &ref_div); fb_div 1047 drivers/gpu/drm/radeon/radeon_display.c diff = abs(target_clock - (pll->reference_freq * fb_div) / fb_div 1061 drivers/gpu/drm/radeon/radeon_display.c &fb_div, &ref_div); fb_div 1065 drivers/gpu/drm/radeon/radeon_display.c avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min); fb_div 1068 drivers/gpu/drm/radeon/radeon_display.c if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) { fb_div 1069 drivers/gpu/drm/radeon/radeon_display.c fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 50); fb_div 1070 drivers/gpu/drm/radeon/radeon_display.c if (fb_div < fb_div_min) { fb_div 1071 drivers/gpu/drm/radeon/radeon_display.c unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div); fb_div 1072 drivers/gpu/drm/radeon/radeon_display.c fb_div *= tmp; fb_div 1079 drivers/gpu/drm/radeon/radeon_display.c *fb_div_p = fb_div / 10; fb_div 1080 drivers/gpu/drm/radeon/radeon_display.c *frac_fb_div_p = fb_div % 10; fb_div 1082 drivers/gpu/drm/radeon/radeon_display.c *fb_div_p = fb_div; fb_div 267 drivers/gpu/drm/radeon/radeon_legacy_crtc.c uint16_t fb_div) fb_div 274 drivers/gpu/drm/radeon/radeon_legacy_crtc.c vcoFreq = ((unsigned)ref_freq * fb_div) / ref_div; fb_div 593 drivers/gpu/drm/radeon/radeon_mode.h u32 fb_div; fb_div 618 drivers/gpu/drm/radeon/radeon_mode.h u32 fb_div; fb_div 978 drivers/gpu/drm/radeon/radeon_uvd.c uint64_t fb_div = (uint64_t)vco_freq * fb_factor; fb_div 981 drivers/gpu/drm/radeon/radeon_uvd.c do_div(fb_div, ref_freq); fb_div 984 drivers/gpu/drm/radeon/radeon_uvd.c if (fb_div > fb_mask) fb_div 987 drivers/gpu/drm/radeon/radeon_uvd.c fb_div &= fb_mask; fb_div 1006 drivers/gpu/drm/radeon/radeon_uvd.c *optimal_fb_div = fb_div; fb_div 89 drivers/gpu/drm/radeon/rs780_dpm.c r600_engine_clock_entry_set_feedback_divider(rdev, 0, dividers.fb_div); fb_div 407 drivers/gpu/drm/radeon/rs780_dpm.c static void rs780_force_fbdiv(struct radeon_device *rdev, u32 fb_div) fb_div 416 drivers/gpu/drm/radeon/rs780_dpm.c WREG32_P(FVTHROT_FBDIV_REG2, FORCED_FEEDBACK_DIV(fb_div), fb_div 418 drivers/gpu/drm/radeon/rs780_dpm.c WREG32_P(FVTHROT_FBDIV_REG1, STARTING_FEEDBACK_DIV(fb_div), fb_div 461 drivers/gpu/drm/radeon/rs780_dpm.c rs780_force_fbdiv(rdev, max_dividers.fb_div); fb_div 463 drivers/gpu/drm/radeon/rs780_dpm.c if (max_dividers.fb_div > min_dividers.fb_div) { fb_div 465 drivers/gpu/drm/radeon/rs780_dpm.c MIN_FEEDBACK_DIV(min_dividers.fb_div) | fb_div 466 drivers/gpu/drm/radeon/rs780_dpm.c MAX_FEEDBACK_DIV(max_dividers.fb_div), fb_div 1050 drivers/gpu/drm/radeon/rs780_dpm.c rs780_force_fbdiv(rdev, dividers.fb_div); fb_div 1057 drivers/gpu/drm/radeon/rs780_dpm.c rs780_force_fbdiv(rdev, dividers.fb_div); fb_div 529 drivers/gpu/drm/radeon/rv6xx_dpm.c return ref_clock * ((dividers->fb_div & ~1) << fb_divider_scale) / fb_div 607 drivers/gpu/drm/radeon/rv6xx_dpm.c rv6xx_memory_clock_entry_set_feedback_divider(rdev, entry, dividers.fb_div); fb_div 159 drivers/gpu/drm/radeon/rv730_dpm.c mpll_func_cntl_3 |= MPLL_FB_DIV(dividers.fb_div); fb_div 173 drivers/gpu/drm/radeon/rv730_dpm.c u32 clk_v = ss.percentage * dividers.fb_div / (clk_s * 10000); fb_div 53 drivers/gpu/drm/radeon/rv770.c unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; fb_div 73 drivers/gpu/drm/radeon/rv770.c &fb_div, &vclk_div, &dclk_div); fb_div 77 drivers/gpu/drm/radeon/rv770.c fb_div |= 1; fb_div 107 drivers/gpu/drm/radeon/rv770.c WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), fb_div 6999 drivers/gpu/drm/radeon/si.c unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; fb_div 7017 drivers/gpu/drm/radeon/si.c &fb_div, &vclk_div, &dclk_div); fb_div 7046 drivers/gpu/drm/radeon/si.c WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), ~UPLL_FB_DIV_MASK); fb_div 7051 drivers/gpu/drm/radeon/si.c if (fb_div < 307200) fb_div 7486 drivers/gpu/drm/radeon/si.c unsigned fb_div = 0, evclk_div = 0, ecclk_div = 0; fb_div 7507 drivers/gpu/drm/radeon/si.c &fb_div, &evclk_div, &ecclk_div); fb_div 7539 drivers/gpu/drm/radeon/si.c WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_3, VCEPLL_FB_DIV(fb_div), ~VCEPLL_FB_DIV_MASK); fb_div 2853 drivers/gpu/drm/radeon/si_dpm.c u32 fb_div, p_div; fb_div 2873 drivers/gpu/drm/radeon/si_dpm.c fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; fb_div 2877 drivers/gpu/drm/radeon/si_dpm.c fb_div &= ~0x00001FFF; fb_div 2878 drivers/gpu/drm/radeon/si_dpm.c fb_div >>= 1; fb_div 2883 drivers/gpu/drm/radeon/si_dpm.c if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT)) fb_div 2893 drivers/gpu/drm/radeon/si_dpm.c tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) | fb_div 1548 drivers/video/fbdev/aty/radeon_base.c int fb_div, pll_output_freq = 0; fb_div 1637 drivers/video/fbdev/aty/radeon_base.c fb_div = round_div(rinfo->pll.ref_div*pll_output_freq, fb_div 1640 drivers/video/fbdev/aty/radeon_base.c regs->ppll_div_3 = fb_div | (post_div->bitvalue << 16); fb_div 1643 drivers/video/fbdev/aty/radeon_base.c pr_debug("fb_div = 0x%x\n", fb_div);