fake_cb_bridge_regs  206 arch/mips/pci/ops-bcm63xx.c } fake_cb_bridge_regs;
fake_cb_bridge_regs  224 arch/mips/pci/ops-bcm63xx.c 		data |= fake_cb_bridge_regs.pci_command;
fake_cb_bridge_regs  237 arch/mips/pci/ops-bcm63xx.c 		data = (fake_cb_bridge_regs.bridge_control << 16);
fake_cb_bridge_regs  243 arch/mips/pci/ops-bcm63xx.c 		data = (fake_cb_bridge_regs.cb_latency << 24);
fake_cb_bridge_regs  244 arch/mips/pci/ops-bcm63xx.c 		data |= (fake_cb_bridge_regs.subordinate_busn << 16);
fake_cb_bridge_regs  245 arch/mips/pci/ops-bcm63xx.c 		data |= (fake_cb_bridge_regs.cardbus_busn << 8);
fake_cb_bridge_regs  246 arch/mips/pci/ops-bcm63xx.c 		data |= fake_cb_bridge_regs.pci_busn;
fake_cb_bridge_regs  250 arch/mips/pci/ops-bcm63xx.c 		data = fake_cb_bridge_regs.mem_base0;
fake_cb_bridge_regs  254 arch/mips/pci/ops-bcm63xx.c 		data = fake_cb_bridge_regs.mem_limit0;
fake_cb_bridge_regs  258 arch/mips/pci/ops-bcm63xx.c 		data = fake_cb_bridge_regs.mem_base1;
fake_cb_bridge_regs  262 arch/mips/pci/ops-bcm63xx.c 		data = fake_cb_bridge_regs.mem_limit1;
fake_cb_bridge_regs  267 arch/mips/pci/ops-bcm63xx.c 		data = fake_cb_bridge_regs.io_base0 | 0x1;
fake_cb_bridge_regs  271 arch/mips/pci/ops-bcm63xx.c 		data = fake_cb_bridge_regs.io_limit0;
fake_cb_bridge_regs  276 arch/mips/pci/ops-bcm63xx.c 		data = fake_cb_bridge_regs.io_base1 | 0x1;
fake_cb_bridge_regs  280 arch/mips/pci/ops-bcm63xx.c 		data = fake_cb_bridge_regs.io_limit1;
fake_cb_bridge_regs  306 arch/mips/pci/ops-bcm63xx.c 		fake_cb_bridge_regs.pci_command = (data & 0xffff);
fake_cb_bridge_regs  310 arch/mips/pci/ops-bcm63xx.c 		fake_cb_bridge_regs.cb_latency = (data >> 24) & 0xff;
fake_cb_bridge_regs  311 arch/mips/pci/ops-bcm63xx.c 		fake_cb_bridge_regs.subordinate_busn = (data >> 16) & 0xff;
fake_cb_bridge_regs  312 arch/mips/pci/ops-bcm63xx.c 		fake_cb_bridge_regs.cardbus_busn = (data >> 8) & 0xff;
fake_cb_bridge_regs  313 arch/mips/pci/ops-bcm63xx.c 		fake_cb_bridge_regs.pci_busn = data & 0xff;
fake_cb_bridge_regs  314 arch/mips/pci/ops-bcm63xx.c 		if (fake_cb_bridge_regs.cardbus_busn)
fake_cb_bridge_regs  315 arch/mips/pci/ops-bcm63xx.c 			fake_cb_bridge_regs.bus_assigned = 1;
fake_cb_bridge_regs  323 arch/mips/pci/ops-bcm63xx.c 		fake_cb_bridge_regs.bridge_control = tmp;
fake_cb_bridge_regs  327 arch/mips/pci/ops-bcm63xx.c 		fake_cb_bridge_regs.mem_base0 = data;
fake_cb_bridge_regs  331 arch/mips/pci/ops-bcm63xx.c 		fake_cb_bridge_regs.mem_limit0 = data;
fake_cb_bridge_regs  335 arch/mips/pci/ops-bcm63xx.c 		fake_cb_bridge_regs.mem_base1 = data;
fake_cb_bridge_regs  339 arch/mips/pci/ops-bcm63xx.c 		fake_cb_bridge_regs.mem_limit1 = data;
fake_cb_bridge_regs  343 arch/mips/pci/ops-bcm63xx.c 		fake_cb_bridge_regs.io_base0 = data;
fake_cb_bridge_regs  347 arch/mips/pci/ops-bcm63xx.c 		fake_cb_bridge_regs.io_limit0 = data;
fake_cb_bridge_regs  351 arch/mips/pci/ops-bcm63xx.c 		fake_cb_bridge_regs.io_base1 = data;
fake_cb_bridge_regs  355 arch/mips/pci/ops-bcm63xx.c 		fake_cb_bridge_regs.io_limit1 = data;
fake_cb_bridge_regs  376 arch/mips/pci/ops-bcm63xx.c 	if (fake_cb_bridge_regs.bus_assigned &&
fake_cb_bridge_regs  377 arch/mips/pci/ops-bcm63xx.c 	    bus->number == fake_cb_bridge_regs.cardbus_busn &&
fake_cb_bridge_regs  394 arch/mips/pci/ops-bcm63xx.c 	if (fake_cb_bridge_regs.bus_assigned &&
fake_cb_bridge_regs  395 arch/mips/pci/ops-bcm63xx.c 	    bus->number == fake_cb_bridge_regs.cardbus_busn &&
fake_cb_bridge_regs  436 arch/mips/pci/ops-bcm63xx.c 	if (fake_cb_bridge_regs.bus_assigned &&
fake_cb_bridge_regs  437 arch/mips/pci/ops-bcm63xx.c 	    dev->bus->number == fake_cb_bridge_regs.cardbus_busn &&