failsafe          287 drivers/cpufreq/speedstep-centrino.c static unsigned extract_clock(unsigned msr, unsigned int cpu, int failsafe)
failsafe          316 drivers/cpufreq/speedstep-centrino.c 	if (failsafe)
failsafe          175 drivers/gpu/drm/i915/gvt/gvt.h 	bool failsafe;
failsafe          189 drivers/gpu/drm/i915/gvt/handlers.c 	vgpu->failsafe = true;
failsafe          109 drivers/gpu/drm/i915/gvt/mmio.c 	if (vgpu->failsafe) {
failsafe          181 drivers/gpu/drm/i915/gvt/mmio.c 	if (vgpu->failsafe) {
failsafe          173 drivers/gpu/drm/i915/gvt/page_track.c 	if (unlikely(vgpu->failsafe)) {
failsafe          574 drivers/gpu/drm/i915/gvt/vgpu.c 			vgpu->failsafe = false;
failsafe          352 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c 	const struct dp_rates *failsafe = NULL, *cfg;
failsafe          372 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c 			if (!failsafe ||
failsafe          374 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c 				failsafe = cfg;
failsafe          377 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c 		if (failsafe && cfg[1].rate < dataKBps)
failsafe          381 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c 	if (WARN_ON(!failsafe))
failsafe          395 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c 		 failsafe->nr, failsafe->bw * 27);
failsafe          397 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c 	for (cfg = nvkm_dp_rates; ret < 0 && cfg <= failsafe; cfg++) {
failsafe          401 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c 			if (cfg != failsafe)