GC_BASE            35 drivers/gpu/drm/amd/amdgpu/arct_reg_init.c 		adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
GC_BASE            35 drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c 		adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
GC_BASE            46 drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c 		adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
GC_BASE            47 drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c 		adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
GC_BASE            35 drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c 		adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
GC_BASE            46 drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c 		adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
GC_BASE            47 drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c 		adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
GC_BASE            35 drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c 		adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
GC_BASE            46 drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c 		adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
GC_BASE            47 drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c 		adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
GC_BASE            35 drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c 		adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
GC_BASE            35 drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c 		adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
GC_BASE            71 drivers/gpu/drm/amd/include/arct_ip_offset.h static const struct IP_BASE GC_BASE            ={ { { { 0x00002000, 0x0000A000, 0x00012160, 0x00402C00, 0, 0 } },
GC_BASE            67 drivers/gpu/drm/amd/include/navi10_ip_offset.h static const struct IP_BASE GC_BASE            ={ { { { 0x00001260, 0x0000A000, 0, 0, 0, 0 } },
GC_BASE            88 drivers/gpu/drm/amd/include/navi12_ip_offset.h static const struct IP_BASE GC_BASE ={ { { { 0x00001260, 0x0000A000, 0x02402C00, 0, 0 } },
GC_BASE            88 drivers/gpu/drm/amd/include/navi14_ip_offset.h static const struct IP_BASE GC_BASE ={ { { { 0x00001260, 0x0000A000, 0x02402C00, 0, 0 } },
GC_BASE           102 drivers/gpu/drm/amd/include/renoir_ip_offset.h static const struct IP_BASE GC_BASE ={ { { { 0x00002000, 0x0000A000, 0x02402C00, 0, 0 } },
GC_BASE           143 drivers/gpu/drm/amd/include/vega10_ip_offset.h static const struct IP_BASE GC_BASE			= { { { { 0x00002000, 0x0000A000, 0, 0, 0 } },
GC_BASE            69 drivers/gpu/drm/amd/include/vega20_ip_offset.h static const struct IP_BASE GC_BASE            ={ { { { 0x00002000, 0x0000A000, 0, 0, 0, 0 } },