GCMC_VM_MX_L1_TLB_CNTL  117 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
GCMC_VM_MX_L1_TLB_CNTL  118 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
GCMC_VM_MX_L1_TLB_CNTL  119 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
GCMC_VM_MX_L1_TLB_CNTL  121 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
GCMC_VM_MX_L1_TLB_CNTL  123 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
GCMC_VM_MX_L1_TLB_CNTL  124 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
GCMC_VM_MX_L1_TLB_CNTL  290 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
GCMC_VM_MX_L1_TLB_CNTL  291 drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c 	tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,