f9 147 arch/ia64/include/uapi/asm/ptrace.h struct ia64_fpreg f9; /* scratch */ f9 122 arch/ia64/kernel/asm-offsets.c DEFINE(IA64_PT_REGS_F9_OFFSET, offsetof (struct pt_regs, f9)); f9 202 arch/ia64/kernel/minstate.h stf.spill [r3]=f9,32; \ f9 124 arch/ia64/kernel/process.c regs->f9.u.bits[1], regs->f9.u.bits[0]); f9 234 arch/ia64/kernel/unaligned.c RPT(f6), RPT(f7), RPT(f8), RPT(f9), f9 117 arch/mips/include/asm/asmmacro.h sdc1 $f9, THREAD_FPR9(\thread) f9 176 arch/mips/include/asm/asmmacro.h ldc1 $f9, THREAD_FPR9(\thread) f9 50 arch/mips/include/asm/fpregdef.h #define ft2f $f9 f9 91 arch/mips/include/asm/fpregdef.h #define ft5 $f9 f9 128 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h v5, f6, v6, f7, v7, f8, v8, f9, v9) \ f9 138 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f9), v9) f9 141 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h v5, f6, v6, f7, v7, f8, v8, f9, v9, f10, v10) \ f9 151 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f9), v9, \ f9 290 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_9(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9) \ f9 300 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f9), v9) f9 302 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_10(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10, v10)\ f9 312 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f9), v9, \ f9 315 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_14(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\ f9 326 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f9), v9, \ f9 333 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_19(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\ f9 344 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f9), v9, \ f9 356 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_20(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\ f9 367 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f9), v9, \ f9 219 drivers/pinctrl/qcom/pinctrl-apq8064.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10) \ f9 234 drivers/pinctrl/qcom/pinctrl-apq8064.c APQ_MUX_##f9, \ f9 226 drivers/pinctrl/qcom/pinctrl-ipq4019.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11, f12, f13, f14) \ f9 241 drivers/pinctrl/qcom/pinctrl-ipq4019.c qca_mux_##f9, \ f9 171 drivers/pinctrl/qcom/pinctrl-ipq8064.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10) \ f9 186 drivers/pinctrl/qcom/pinctrl-ipq8064.c IPQ_MUX_##f9, \ f9 21 drivers/pinctrl/qcom/pinctrl-ipq8074.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ f9 36 drivers/pinctrl/qcom/pinctrl-ipq8074.c msm_mux_##f9 \ f9 205 drivers/pinctrl/qcom/pinctrl-mdm9615.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \ f9 220 drivers/pinctrl/qcom/pinctrl-mdm9615.c MSM_MUX_##f9, \ f9 296 drivers/pinctrl/qcom/pinctrl-msm8916.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ f9 311 drivers/pinctrl/qcom/pinctrl-msm8916.c MSM_MUX_##f9 \ f9 344 drivers/pinctrl/qcom/pinctrl-msm8960.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \ f9 359 drivers/pinctrl/qcom/pinctrl-msm8960.c MSM_MUX_##f9, \ f9 20 drivers/pinctrl/qcom/pinctrl-msm8994.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \ f9 35 drivers/pinctrl/qcom/pinctrl-msm8994.c MSM_MUX_##f9, \ f9 22 drivers/pinctrl/qcom/pinctrl-msm8996.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ f9 37 drivers/pinctrl/qcom/pinctrl-msm8996.c msm_mux_##f9 \ f9 24 drivers/pinctrl/qcom/pinctrl-msm8998.c #define PINGROUP(id, base, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ f9 39 drivers/pinctrl/qcom/pinctrl-msm8998.c msm_mux_##f9 \ f9 32 drivers/pinctrl/qcom/pinctrl-qcs404.c #define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ f9 47 drivers/pinctrl/qcom/pinctrl-qcs404.c msm_mux_##f9 \ f9 30 drivers/pinctrl/qcom/pinctrl-sc7180.c #define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ f9 45 drivers/pinctrl/qcom/pinctrl-sc7180.c msm_mux_##f9 \ f9 36 drivers/pinctrl/qcom/pinctrl-sdm660.c #define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ f9 51 drivers/pinctrl/qcom/pinctrl-sdm660.c msm_mux_##f9 \ f9 25 drivers/pinctrl/qcom/pinctrl-sdm845.c #define PINGROUP(id, base, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10) \ f9 40 drivers/pinctrl/qcom/pinctrl-sdm845.c msm_mux_##f9, \ f9 32 drivers/pinctrl/qcom/pinctrl-sm8150.c #define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ f9 47 drivers/pinctrl/qcom/pinctrl-sm8150.c msm_mux_##f9 \ f9 23 tools/perf/arch/s390/include/dwarf-regs-table.h REG_DWARFNUM_NAME(f9, 28),