f8 146 arch/ia64/include/uapi/asm/ptrace.h struct ia64_fpreg f8; /* scratch */ f8 121 arch/ia64/kernel/asm-offsets.c DEFINE(IA64_PT_REGS_F8_OFFSET, offsetof (struct pt_regs, f8)); f8 201 arch/ia64/kernel/minstate.h stf.spill [r2]=f8,32; \ f8 123 arch/ia64/kernel/process.c regs->f8.u.bits[1], regs->f8.u.bits[0], f8 234 arch/ia64/kernel/unaligned.c RPT(f6), RPT(f7), RPT(f8), RPT(f9), f8 24 arch/mips/include/asm/asmmacro-32.h s.d $f8, THREAD_FPR8(\thread) f8 48 arch/mips/include/asm/asmmacro-32.h l.d $f8, THREAD_FPR8(\thread) f8 92 arch/mips/include/asm/asmmacro.h sdc1 $f8, THREAD_FPR8(\thread) f8 151 arch/mips/include/asm/asmmacro.h ldc1 $f8, THREAD_FPR8(\thread) f8 49 arch/mips/include/asm/fpregdef.h #define ft2 $f8 f8 90 arch/mips/include/asm/fpregdef.h #define ft4 $f8 f8 116 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h f5, v5, f6, v6, f7, v7, f8, v8) \ f8 125 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f8), v8) f8 128 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h v5, f6, v6, f7, v7, f8, v8, f9, v9) \ f8 137 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f8), v8, \ f8 141 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h v5, f6, v6, f7, v7, f8, v8, f9, v9, f10, v10) \ f8 150 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f8), v8, \ f8 205 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_GET_8(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \ f8 214 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, f8), v8) f8 279 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_8(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \ f8 288 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f8), v8) f8 290 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_9(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9) \ f8 299 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f8), v8, \ f8 302 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_10(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10, v10)\ f8 311 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f8), v8, \ f8 315 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_14(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\ f8 325 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f8), v8, \ f8 333 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_19(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\ f8 343 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f8), v8, \ f8 356 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_20(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\ f8 366 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f8), v8, \ f8 219 drivers/pinctrl/qcom/pinctrl-apq8064.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10) \ f8 233 drivers/pinctrl/qcom/pinctrl-apq8064.c APQ_MUX_##f8, \ f8 226 drivers/pinctrl/qcom/pinctrl-ipq4019.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11, f12, f13, f14) \ f8 240 drivers/pinctrl/qcom/pinctrl-ipq4019.c qca_mux_##f8, \ f8 171 drivers/pinctrl/qcom/pinctrl-ipq8064.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10) \ f8 185 drivers/pinctrl/qcom/pinctrl-ipq8064.c IPQ_MUX_##f8, \ f8 21 drivers/pinctrl/qcom/pinctrl-ipq8074.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ f8 35 drivers/pinctrl/qcom/pinctrl-ipq8074.c msm_mux_##f8, \ f8 205 drivers/pinctrl/qcom/pinctrl-mdm9615.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \ f8 219 drivers/pinctrl/qcom/pinctrl-mdm9615.c MSM_MUX_##f8, \ f8 296 drivers/pinctrl/qcom/pinctrl-msm8916.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ f8 310 drivers/pinctrl/qcom/pinctrl-msm8916.c MSM_MUX_##f8, \ f8 344 drivers/pinctrl/qcom/pinctrl-msm8960.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \ f8 358 drivers/pinctrl/qcom/pinctrl-msm8960.c MSM_MUX_##f8, \ f8 20 drivers/pinctrl/qcom/pinctrl-msm8994.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \ f8 34 drivers/pinctrl/qcom/pinctrl-msm8994.c MSM_MUX_##f8, \ f8 22 drivers/pinctrl/qcom/pinctrl-msm8996.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ f8 36 drivers/pinctrl/qcom/pinctrl-msm8996.c msm_mux_##f8, \ f8 24 drivers/pinctrl/qcom/pinctrl-msm8998.c #define PINGROUP(id, base, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ f8 38 drivers/pinctrl/qcom/pinctrl-msm8998.c msm_mux_##f8, \ f8 32 drivers/pinctrl/qcom/pinctrl-qcs404.c #define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ f8 46 drivers/pinctrl/qcom/pinctrl-qcs404.c msm_mux_##f8, \ f8 30 drivers/pinctrl/qcom/pinctrl-sc7180.c #define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ f8 44 drivers/pinctrl/qcom/pinctrl-sc7180.c msm_mux_##f8, \ f8 36 drivers/pinctrl/qcom/pinctrl-sdm660.c #define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ f8 50 drivers/pinctrl/qcom/pinctrl-sdm660.c msm_mux_##f8, \ f8 25 drivers/pinctrl/qcom/pinctrl-sdm845.c #define PINGROUP(id, base, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10) \ f8 39 drivers/pinctrl/qcom/pinctrl-sdm845.c msm_mux_##f8, \ f8 32 drivers/pinctrl/qcom/pinctrl-sm8150.c #define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ f8 46 drivers/pinctrl/qcom/pinctrl-sm8150.c msm_mux_##f8, \ f8 325 mm/kasan/generic.c DEFINE_ASAN_SET_SHADOW(f8); f8 22 tools/perf/arch/s390/include/dwarf-regs-table.h REG_DWARFNUM_NAME(f8, 24),