f7 145 arch/ia64/include/uapi/asm/ptrace.h struct ia64_fpreg f7; /* scratch */ f7 120 arch/ia64/kernel/asm-offsets.c DEFINE(IA64_PT_REGS_F7_OFFSET, offsetof (struct pt_regs, f7)); f7 199 arch/ia64/kernel/minstate.h stf.spill [r3]=f7,32; \ f7 121 arch/ia64/kernel/process.c regs->f7.u.bits[1], regs->f7.u.bits[0]); f7 234 arch/ia64/kernel/unaligned.c RPT(f6), RPT(f7), RPT(f8), RPT(f9), f7 116 arch/mips/include/asm/asmmacro.h sdc1 $f7, THREAD_FPR7(\thread) f7 175 arch/mips/include/asm/asmmacro.h ldc1 $f7, THREAD_FPR7(\thread) f7 48 arch/mips/include/asm/fpregdef.h #define ft1f $f7 f7 89 arch/mips/include/asm/fpregdef.h #define ft3 $f7 f7 198 drivers/block/paride/bpck.c { int o1, o0, f7, id; f7 209 drivers/block/paride/bpck.c f7 = ((id % 8) == 7); f7 210 drivers/block/paride/bpck.c if ((f7) || (t != o1)) { t2(2); s = r1()&0xf8; } f7 211 drivers/block/paride/bpck.c if ((t == o1) && ((!f7) || (s == o1))) { f7 105 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h f5, v5, f6, v6, f7, v7) \ f7 113 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f7), v7) f7 116 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h f5, v5, f6, v6, f7, v7, f8, v8) \ f7 124 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f7), v7,\ f7 128 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h v5, f6, v6, f7, v7, f8, v8, f9, v9) \ f7 136 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f7), v7, \ f7 141 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h v5, f6, v6, f7, v7, f8, v8, f9, v9, f10, v10) \ f7 149 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f7), v7, \ f7 195 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_GET_7(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \ f7 203 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, f7), v7) f7 205 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_GET_8(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \ f7 213 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, f7), v7, \ f7 269 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_7(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \ f7 277 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f7), v7) f7 279 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_8(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \ f7 287 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f7), v7, \ f7 290 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_9(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9) \ f7 298 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f7), v7, \ f7 302 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_10(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10, v10)\ f7 310 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f7), v7, \ f7 315 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_14(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\ f7 324 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f7), v7, \ f7 333 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_19(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\ f7 342 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f7), v7, \ f7 356 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_20(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\ f7 365 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f7), v7, \ f7 211 drivers/pinctrl/pinctrl-lpc18xx.c #define LPC_P(port, pin, f0, f1, f2, f3, f4, f5, f6, f7, a, t) \ f7 217 drivers/pinctrl/pinctrl-lpc18xx.c FUNC_##f6, FUNC_##f7, \ f7 223 drivers/pinctrl/pinctrl-lpc18xx.c #define LPC_N(pname, off, f0, f1, f2, f3, f4, f5, f6, f7, a, t) \ f7 229 drivers/pinctrl/pinctrl-lpc18xx.c FUNC_##f6, FUNC_##f7, \ f7 219 drivers/pinctrl/qcom/pinctrl-apq8064.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10) \ f7 232 drivers/pinctrl/qcom/pinctrl-apq8064.c APQ_MUX_##f7, \ f7 334 drivers/pinctrl/qcom/pinctrl-apq8084.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7) \ f7 347 drivers/pinctrl/qcom/pinctrl-apq8084.c APQ_MUX_##f7 \ f7 226 drivers/pinctrl/qcom/pinctrl-ipq4019.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11, f12, f13, f14) \ f7 239 drivers/pinctrl/qcom/pinctrl-ipq4019.c qca_mux_##f7, \ f7 171 drivers/pinctrl/qcom/pinctrl-ipq8064.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10) \ f7 184 drivers/pinctrl/qcom/pinctrl-ipq8064.c IPQ_MUX_##f7, \ f7 21 drivers/pinctrl/qcom/pinctrl-ipq8074.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ f7 34 drivers/pinctrl/qcom/pinctrl-ipq8074.c msm_mux_##f7, \ f7 205 drivers/pinctrl/qcom/pinctrl-mdm9615.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \ f7 218 drivers/pinctrl/qcom/pinctrl-mdm9615.c MSM_MUX_##f7, \ f7 385 drivers/pinctrl/qcom/pinctrl-msm8660.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7) \ f7 398 drivers/pinctrl/qcom/pinctrl-msm8660.c MSM_MUX_##f7, \ f7 296 drivers/pinctrl/qcom/pinctrl-msm8916.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ f7 309 drivers/pinctrl/qcom/pinctrl-msm8916.c MSM_MUX_##f7, \ f7 344 drivers/pinctrl/qcom/pinctrl-msm8960.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \ f7 357 drivers/pinctrl/qcom/pinctrl-msm8960.c MSM_MUX_##f7, \ f7 20 drivers/pinctrl/qcom/pinctrl-msm8994.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \ f7 33 drivers/pinctrl/qcom/pinctrl-msm8994.c MSM_MUX_##f7, \ f7 22 drivers/pinctrl/qcom/pinctrl-msm8996.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ f7 35 drivers/pinctrl/qcom/pinctrl-msm8996.c msm_mux_##f7, \ f7 24 drivers/pinctrl/qcom/pinctrl-msm8998.c #define PINGROUP(id, base, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ f7 37 drivers/pinctrl/qcom/pinctrl-msm8998.c msm_mux_##f7, \ f7 335 drivers/pinctrl/qcom/pinctrl-msm8x74.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7) \ f7 348 drivers/pinctrl/qcom/pinctrl-msm8x74.c MSM_MUX_##f7 \ f7 32 drivers/pinctrl/qcom/pinctrl-qcs404.c #define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ f7 45 drivers/pinctrl/qcom/pinctrl-qcs404.c msm_mux_##f7, \ f7 30 drivers/pinctrl/qcom/pinctrl-sc7180.c #define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ f7 43 drivers/pinctrl/qcom/pinctrl-sc7180.c msm_mux_##f7, \ f7 36 drivers/pinctrl/qcom/pinctrl-sdm660.c #define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ f7 49 drivers/pinctrl/qcom/pinctrl-sdm660.c msm_mux_##f7, \ f7 25 drivers/pinctrl/qcom/pinctrl-sdm845.c #define PINGROUP(id, base, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10) \ f7 38 drivers/pinctrl/qcom/pinctrl-sdm845.c msm_mux_##f7, \ f7 32 drivers/pinctrl/qcom/pinctrl-sm8150.c #define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ f7 45 drivers/pinctrl/qcom/pinctrl-sm8150.c msm_mux_##f7, \ f7 424 drivers/pinctrl/sh-pfc/pfc-r8a77990.c #define REV8(f0, f1, f2, f3, f4, f5, f6, f7) f0 f4 f2 f6 f1 f5 f3 f7 f7 21 tools/perf/arch/s390/include/dwarf-regs-table.h REG_DWARFNUM_NAME(f7, 23),