f6 144 arch/ia64/include/uapi/asm/ptrace.h struct ia64_fpreg f6; /* scratch */ f6 119 arch/ia64/kernel/asm-offsets.c DEFINE(IA64_PT_REGS_F6_OFFSET, offsetof (struct pt_regs, f6)); f6 198 arch/ia64/kernel/minstate.h stf.spill [r2]=f6,32; \ f6 120 arch/ia64/kernel/process.c regs->f6.u.bits[1], regs->f6.u.bits[0], f6 781 arch/ia64/kernel/ptrace.c memset(&pt->f6, 0, 6*16); /* clear f6-f11 */ f6 937 arch/ia64/kernel/ptrace.c retval |= __copy_to_user(&ppr->fr[6], &pt->f6, f6 1073 arch/ia64/kernel/ptrace.c retval |= __copy_from_user(&pt->f6, &ppr->fr[6], f6 251 arch/ia64/kernel/traps.c fp_state.fp_state_low_volatile = (fp_state_low_volatile_t *) ®s->f6; f6 234 arch/ia64/kernel/unaligned.c RPT(f6), RPT(f7), RPT(f8), RPT(f9), f6 464 arch/ia64/kernel/unwind.c addr = &pt->f6 + (regnum - 6); f6 1446 arch/ia64/kernel/unwind.c val = offsetof(struct pt_regs, f6) + 16*(rval - 6); f6 23 arch/mips/include/asm/asmmacro-32.h s.d $f6, THREAD_FPR6(\thread) f6 47 arch/mips/include/asm/asmmacro-32.h l.d $f6, THREAD_FPR6(\thread) f6 91 arch/mips/include/asm/asmmacro.h sdc1 $f6, THREAD_FPR6(\thread) f6 150 arch/mips/include/asm/asmmacro.h ldc1 $f6, THREAD_FPR6(\thread) f6 47 arch/mips/include/asm/fpregdef.h #define ft1 $f6 f6 88 arch/mips/include/asm/fpregdef.h #define ft2 $f6 f6 95 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h f5, v5, f6, v6) \ f6 102 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f6), v6) f6 105 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h f5, v5, f6, v6, f7, v7) \ f6 112 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f6), v6,\ f6 116 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h f5, v5, f6, v6, f7, v7, f8, v8) \ f6 123 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f6), v6,\ f6 128 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h v5, f6, v6, f7, v7, f8, v8, f9, v9) \ f6 135 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f6), v6, \ f6 141 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h v5, f6, v6, f7, v7, f8, v8, f9, v9, f10, v10) \ f6 148 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f6), v6, \ f6 186 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_GET_6(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \ f6 193 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, f6), v6) f6 195 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_GET_7(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \ f6 202 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, f6), v6, \ f6 205 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_GET_8(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \ f6 212 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, f6), v6, \ f6 260 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_6(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \ f6 267 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f6), v6) f6 269 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_7(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \ f6 276 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f6), v6, \ f6 279 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_8(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \ f6 286 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f6), v6, \ f6 290 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_9(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9) \ f6 297 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f6), v6, \ f6 302 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_10(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10, v10)\ f6 309 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f6), v6, \ f6 315 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_14(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\ f6 323 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f6), v6, \ f6 333 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_19(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\ f6 341 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f6), v6, \ f6 356 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_20(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\ f6 364 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f6), v6, \ f6 211 drivers/pinctrl/pinctrl-lpc18xx.c #define LPC_P(port, pin, f0, f1, f2, f3, f4, f5, f6, f7, a, t) \ f6 217 drivers/pinctrl/pinctrl-lpc18xx.c FUNC_##f6, FUNC_##f7, \ f6 223 drivers/pinctrl/pinctrl-lpc18xx.c #define LPC_N(pname, off, f0, f1, f2, f3, f4, f5, f6, f7, a, t) \ f6 229 drivers/pinctrl/pinctrl-lpc18xx.c FUNC_##f6, FUNC_##f7, \ f6 219 drivers/pinctrl/qcom/pinctrl-apq8064.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10) \ f6 231 drivers/pinctrl/qcom/pinctrl-apq8064.c APQ_MUX_##f6, \ f6 334 drivers/pinctrl/qcom/pinctrl-apq8084.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7) \ f6 346 drivers/pinctrl/qcom/pinctrl-apq8084.c APQ_MUX_##f6, \ f6 226 drivers/pinctrl/qcom/pinctrl-ipq4019.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11, f12, f13, f14) \ f6 238 drivers/pinctrl/qcom/pinctrl-ipq4019.c qca_mux_##f6, \ f6 171 drivers/pinctrl/qcom/pinctrl-ipq8064.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10) \ f6 183 drivers/pinctrl/qcom/pinctrl-ipq8064.c IPQ_MUX_##f6, \ f6 21 drivers/pinctrl/qcom/pinctrl-ipq8074.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ f6 33 drivers/pinctrl/qcom/pinctrl-ipq8074.c msm_mux_##f6, \ f6 205 drivers/pinctrl/qcom/pinctrl-mdm9615.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \ f6 217 drivers/pinctrl/qcom/pinctrl-mdm9615.c MSM_MUX_##f6, \ f6 385 drivers/pinctrl/qcom/pinctrl-msm8660.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7) \ f6 397 drivers/pinctrl/qcom/pinctrl-msm8660.c MSM_MUX_##f6, \ f6 296 drivers/pinctrl/qcom/pinctrl-msm8916.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ f6 308 drivers/pinctrl/qcom/pinctrl-msm8916.c MSM_MUX_##f6, \ f6 344 drivers/pinctrl/qcom/pinctrl-msm8960.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \ f6 356 drivers/pinctrl/qcom/pinctrl-msm8960.c MSM_MUX_##f6, \ f6 20 drivers/pinctrl/qcom/pinctrl-msm8994.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \ f6 32 drivers/pinctrl/qcom/pinctrl-msm8994.c MSM_MUX_##f6, \ f6 22 drivers/pinctrl/qcom/pinctrl-msm8996.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ f6 34 drivers/pinctrl/qcom/pinctrl-msm8996.c msm_mux_##f6, \ f6 24 drivers/pinctrl/qcom/pinctrl-msm8998.c #define PINGROUP(id, base, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ f6 36 drivers/pinctrl/qcom/pinctrl-msm8998.c msm_mux_##f6, \ f6 335 drivers/pinctrl/qcom/pinctrl-msm8x74.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7) \ f6 347 drivers/pinctrl/qcom/pinctrl-msm8x74.c MSM_MUX_##f6, \ f6 32 drivers/pinctrl/qcom/pinctrl-qcs404.c #define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ f6 44 drivers/pinctrl/qcom/pinctrl-qcs404.c msm_mux_##f6, \ f6 30 drivers/pinctrl/qcom/pinctrl-sc7180.c #define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ f6 42 drivers/pinctrl/qcom/pinctrl-sc7180.c msm_mux_##f6, \ f6 36 drivers/pinctrl/qcom/pinctrl-sdm660.c #define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ f6 48 drivers/pinctrl/qcom/pinctrl-sdm660.c msm_mux_##f6, \ f6 25 drivers/pinctrl/qcom/pinctrl-sdm845.c #define PINGROUP(id, base, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10) \ f6 37 drivers/pinctrl/qcom/pinctrl-sdm845.c msm_mux_##f6, \ f6 32 drivers/pinctrl/qcom/pinctrl-sm8150.c #define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ f6 44 drivers/pinctrl/qcom/pinctrl-sm8150.c msm_mux_##f6, \ f6 424 drivers/pinctrl/sh-pfc/pfc-r8a77990.c #define REV8(f0, f1, f2, f3, f4, f5, f6, f7) f0 f4 f2 f6 f1 f5 f3 f7 f6 20 tools/perf/arch/s390/include/dwarf-regs-table.h REG_DWARFNUM_NAME(f6, 19),