f5 164 arch/ia64/include/uapi/asm/ptrace.h struct ia64_fpreg f5; /* preserved */ f5 133 arch/ia64/kernel/asm-offsets.c DEFINE(IA64_SWITCH_STACK_F5_OFFSET, offsetof (struct switch_stack, f5)); f5 46 arch/ia64/kernel/entry.h .spillsp f4,SW(F4)+16+(off); .spillsp f5,SW(F5)+16+(off); \ f5 232 arch/ia64/kernel/unaligned.c RSW(f2), RSW(f3), RSW(f4), RSW(f5), f5 115 arch/mips/include/asm/asmmacro.h sdc1 $f5, THREAD_FPR5(\thread) f5 174 arch/mips/include/asm/asmmacro.h ldc1 $f5, THREAD_FPR5(\thread) f5 46 arch/mips/include/asm/fpregdef.h #define ft0f $f5 f5 87 arch/mips/include/asm/fpregdef.h #define ft1 $f5 f5 86 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h f5, v5) \ f5 92 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f5), v5) f5 95 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h f5, v5, f6, v6) \ f5 101 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f5), v5,\ f5 105 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h f5, v5, f6, v6, f7, v7) \ f5 111 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f5), v5,\ f5 116 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h f5, v5, f6, v6, f7, v7, f8, v8) \ f5 122 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f5), v5,\ f5 127 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_SET_9(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, f5, \ f5 134 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f5), v5, \ f5 140 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_SET_10(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, f5, \ f5 147 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f5), v5, \ f5 178 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_GET_5(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \ f5 184 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, f5), v5) f5 186 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_GET_6(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \ f5 192 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, f5), v5, \ f5 195 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_GET_7(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \ f5 201 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, f5), v5, \ f5 205 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_GET_8(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \ f5 211 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, f5), v5, \ f5 252 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_5(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \ f5 258 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f5), v5) f5 260 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_6(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \ f5 266 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f5), v5, \ f5 269 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_7(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \ f5 275 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f5), v5, \ f5 279 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_8(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \ f5 285 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f5), v5, \ f5 290 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_9(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9) \ f5 296 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f5), v5, \ f5 302 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_10(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10, v10)\ f5 308 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f5), v5, \ f5 315 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_14(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\ f5 322 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f5), v5, \ f5 333 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_19(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\ f5 340 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f5), v5, \ f5 356 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_20(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\ f5 363 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f5), v5, \ f5 211 drivers/pinctrl/pinctrl-lpc18xx.c #define LPC_P(port, pin, f0, f1, f2, f3, f4, f5, f6, f7, a, t) \ f5 216 drivers/pinctrl/pinctrl-lpc18xx.c FUNC_##f3, FUNC_##f4, FUNC_##f5, \ f5 223 drivers/pinctrl/pinctrl-lpc18xx.c #define LPC_N(pname, off, f0, f1, f2, f3, f4, f5, f6, f7, a, t) \ f5 228 drivers/pinctrl/pinctrl-lpc18xx.c FUNC_##f3, FUNC_##f4, FUNC_##f5, \ f5 219 drivers/pinctrl/qcom/pinctrl-apq8064.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10) \ f5 230 drivers/pinctrl/qcom/pinctrl-apq8064.c APQ_MUX_##f5, \ f5 334 drivers/pinctrl/qcom/pinctrl-apq8084.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7) \ f5 345 drivers/pinctrl/qcom/pinctrl-apq8084.c APQ_MUX_##f5, \ f5 226 drivers/pinctrl/qcom/pinctrl-ipq4019.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11, f12, f13, f14) \ f5 237 drivers/pinctrl/qcom/pinctrl-ipq4019.c qca_mux_##f5, \ f5 171 drivers/pinctrl/qcom/pinctrl-ipq8064.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10) \ f5 182 drivers/pinctrl/qcom/pinctrl-ipq8064.c IPQ_MUX_##f5, \ f5 21 drivers/pinctrl/qcom/pinctrl-ipq8074.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ f5 32 drivers/pinctrl/qcom/pinctrl-ipq8074.c msm_mux_##f5, \ f5 205 drivers/pinctrl/qcom/pinctrl-mdm9615.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \ f5 216 drivers/pinctrl/qcom/pinctrl-mdm9615.c MSM_MUX_##f5, \ f5 385 drivers/pinctrl/qcom/pinctrl-msm8660.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7) \ f5 396 drivers/pinctrl/qcom/pinctrl-msm8660.c MSM_MUX_##f5, \ f5 296 drivers/pinctrl/qcom/pinctrl-msm8916.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ f5 307 drivers/pinctrl/qcom/pinctrl-msm8916.c MSM_MUX_##f5, \ f5 344 drivers/pinctrl/qcom/pinctrl-msm8960.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \ f5 355 drivers/pinctrl/qcom/pinctrl-msm8960.c MSM_MUX_##f5, \ f5 20 drivers/pinctrl/qcom/pinctrl-msm8994.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \ f5 31 drivers/pinctrl/qcom/pinctrl-msm8994.c MSM_MUX_##f5, \ f5 22 drivers/pinctrl/qcom/pinctrl-msm8996.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ f5 33 drivers/pinctrl/qcom/pinctrl-msm8996.c msm_mux_##f5, \ f5 24 drivers/pinctrl/qcom/pinctrl-msm8998.c #define PINGROUP(id, base, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ f5 35 drivers/pinctrl/qcom/pinctrl-msm8998.c msm_mux_##f5, \ f5 335 drivers/pinctrl/qcom/pinctrl-msm8x74.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7) \ f5 346 drivers/pinctrl/qcom/pinctrl-msm8x74.c MSM_MUX_##f5, \ f5 32 drivers/pinctrl/qcom/pinctrl-qcs404.c #define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ f5 43 drivers/pinctrl/qcom/pinctrl-qcs404.c msm_mux_##f5, \ f5 30 drivers/pinctrl/qcom/pinctrl-sc7180.c #define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ f5 41 drivers/pinctrl/qcom/pinctrl-sc7180.c msm_mux_##f5, \ f5 36 drivers/pinctrl/qcom/pinctrl-sdm660.c #define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ f5 47 drivers/pinctrl/qcom/pinctrl-sdm660.c msm_mux_##f5, \ f5 25 drivers/pinctrl/qcom/pinctrl-sdm845.c #define PINGROUP(id, base, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10) \ f5 36 drivers/pinctrl/qcom/pinctrl-sdm845.c msm_mux_##f5, \ f5 32 drivers/pinctrl/qcom/pinctrl-sm8150.c #define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ f5 43 drivers/pinctrl/qcom/pinctrl-sm8150.c msm_mux_##f5, \ f5 424 drivers/pinctrl/sh-pfc/pfc-r8a77990.c #define REV8(f0, f1, f2, f3, f4, f5, f6, f7) f0 f4 f2 f6 f1 f5 f3 f7 f5 294 drivers/s390/block/dasd_eckd.h __u8 f5; f5 324 mm/kasan/generic.c DEFINE_ASAN_SET_SHADOW(f5); f5 19 tools/perf/arch/s390/include/dwarf-regs-table.h REG_DWARFNUM_NAME(f5, 22),