f4 163 arch/ia64/include/uapi/asm/ptrace.h struct ia64_fpreg f4; /* preserved */ f4 132 arch/ia64/kernel/asm-offsets.c DEFINE(IA64_SWITCH_STACK_F4_OFFSET, offsetof (struct switch_stack, f4)); f4 46 arch/ia64/kernel/entry.h .spillsp f4,SW(F4)+16+(off); .spillsp f5,SW(F5)+16+(off); \ f4 232 arch/ia64/kernel/unaligned.c RSW(f2), RSW(f3), RSW(f4), RSW(f5), f4 22 arch/mips/include/asm/asmmacro-32.h s.d $f4, THREAD_FPR4(\thread) f4 46 arch/mips/include/asm/asmmacro-32.h l.d $f4, THREAD_FPR4(\thread) f4 90 arch/mips/include/asm/asmmacro.h sdc1 $f4, THREAD_FPR4(\thread) f4 149 arch/mips/include/asm/asmmacro.h ldc1 $f4, THREAD_FPR4(\thread) f4 45 arch/mips/include/asm/fpregdef.h #define ft0 $f4 /* caller saved */ f4 86 arch/mips/include/asm/fpregdef.h #define ft0 $f4 /* caller saved */ f4 1384 arch/sparc/include/asm/hypervisor.h unsigned long f4; /* Entry specific */ f4 78 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_SET_4(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4) \ f4 83 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f4), v4) f4 85 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_SET_5(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, \ f4 91 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f4), v4,\ f4 94 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_SET_6(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, \ f4 100 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f4), v4,\ f4 104 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_SET_7(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, \ f4 110 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f4), v4,\ f4 115 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_SET_8(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, \ f4 121 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f4), v4,\ f4 127 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_SET_9(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, f5, \ f4 133 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f4), v4, \ f4 140 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_SET_10(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, f5, \ f4 146 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f4), v4, \ f4 171 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_GET_4(reg_name, f1, v1, f2, v2, f3, v3, f4, v4) \ f4 176 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, f4), v4) f4 178 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_GET_5(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \ f4 183 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, f4), v4, \ f4 186 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_GET_6(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \ f4 191 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, f4), v4, \ f4 195 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_GET_7(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \ f4 200 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, f4), v4, \ f4 205 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_GET_8(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \ f4 210 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg_name, f4), v4, \ f4 245 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_4(reg, f1, v1, f2, v2, f3, v3, f4, v4) \ f4 250 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f4), v4) f4 252 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_5(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \ f4 257 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f4), v4, \ f4 260 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_6(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \ f4 265 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f4), v4, \ f4 269 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_7(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \ f4 274 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f4), v4, \ f4 279 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_8(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \ f4 284 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f4), v4, \ f4 290 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_9(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9) \ f4 295 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f4), v4, \ f4 302 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_10(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10, v10)\ f4 307 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f4), v4, \ f4 315 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_14(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\ f4 321 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f4), v4, \ f4 333 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_19(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\ f4 339 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f4), v4, \ f4 356 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_20(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\ f4 362 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h FN(reg, f4), v4, \ f4 256 drivers/gpu/drm/msm/edp/edp_ctrl.c goto f4; f4 262 drivers/gpu/drm/msm/edp/edp_ctrl.c f4: f4 81 drivers/hwmon/fam15h_power.c struct pci_dev *f4 = data->pdev; f4 83 drivers/hwmon/fam15h_power.c pci_bus_read_config_dword(f4->bus, PCI_DEVFN(PCI_SLOT(f4->devfn), 5), f4 100 drivers/hwmon/fam15h_power.c pci_bus_read_config_dword(f4->bus, PCI_DEVFN(PCI_SLOT(f4->devfn), 5), f4 333 drivers/hwmon/fam15h_power.c static bool should_load_on_this_node(struct pci_dev *f4) f4 337 drivers/hwmon/fam15h_power.c pci_bus_read_config_dword(f4->bus, PCI_DEVFN(PCI_SLOT(f4->devfn), 3), f4 390 drivers/hwmon/fam15h_power.c static int fam15h_power_init_data(struct pci_dev *f4, f4 397 drivers/hwmon/fam15h_power.c pci_read_config_dword(f4, REG_PROCESSOR_TDP, &val); f4 401 drivers/hwmon/fam15h_power.c pci_bus_read_config_dword(f4->bus, PCI_DEVFN(PCI_SLOT(f4->devfn), 5), f4 409 drivers/hwmon/fam15h_power.c dev_warn(&f4->dev, f4 416 drivers/hwmon/fam15h_power.c ret = fam15h_power_init_attrs(f4, data); f4 211 drivers/pinctrl/pinctrl-lpc18xx.c #define LPC_P(port, pin, f0, f1, f2, f3, f4, f5, f6, f7, a, t) \ f4 216 drivers/pinctrl/pinctrl-lpc18xx.c FUNC_##f3, FUNC_##f4, FUNC_##f5, \ f4 223 drivers/pinctrl/pinctrl-lpc18xx.c #define LPC_N(pname, off, f0, f1, f2, f3, f4, f5, f6, f7, a, t) \ f4 228 drivers/pinctrl/pinctrl-lpc18xx.c FUNC_##f3, FUNC_##f4, FUNC_##f5, \ f4 219 drivers/pinctrl/qcom/pinctrl-apq8064.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10) \ f4 229 drivers/pinctrl/qcom/pinctrl-apq8064.c APQ_MUX_##f4, \ f4 334 drivers/pinctrl/qcom/pinctrl-apq8084.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7) \ f4 344 drivers/pinctrl/qcom/pinctrl-apq8084.c APQ_MUX_##f4, \ f4 226 drivers/pinctrl/qcom/pinctrl-ipq4019.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11, f12, f13, f14) \ f4 236 drivers/pinctrl/qcom/pinctrl-ipq4019.c qca_mux_##f4, \ f4 171 drivers/pinctrl/qcom/pinctrl-ipq8064.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10) \ f4 181 drivers/pinctrl/qcom/pinctrl-ipq8064.c IPQ_MUX_##f4, \ f4 21 drivers/pinctrl/qcom/pinctrl-ipq8074.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ f4 31 drivers/pinctrl/qcom/pinctrl-ipq8074.c msm_mux_##f4, \ f4 205 drivers/pinctrl/qcom/pinctrl-mdm9615.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \ f4 215 drivers/pinctrl/qcom/pinctrl-mdm9615.c MSM_MUX_##f4, \ f4 385 drivers/pinctrl/qcom/pinctrl-msm8660.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7) \ f4 395 drivers/pinctrl/qcom/pinctrl-msm8660.c MSM_MUX_##f4, \ f4 296 drivers/pinctrl/qcom/pinctrl-msm8916.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ f4 306 drivers/pinctrl/qcom/pinctrl-msm8916.c MSM_MUX_##f4, \ f4 344 drivers/pinctrl/qcom/pinctrl-msm8960.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \ f4 354 drivers/pinctrl/qcom/pinctrl-msm8960.c MSM_MUX_##f4, \ f4 20 drivers/pinctrl/qcom/pinctrl-msm8994.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \ f4 30 drivers/pinctrl/qcom/pinctrl-msm8994.c MSM_MUX_##f4, \ f4 22 drivers/pinctrl/qcom/pinctrl-msm8996.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ f4 32 drivers/pinctrl/qcom/pinctrl-msm8996.c msm_mux_##f4, \ f4 24 drivers/pinctrl/qcom/pinctrl-msm8998.c #define PINGROUP(id, base, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ f4 34 drivers/pinctrl/qcom/pinctrl-msm8998.c msm_mux_##f4, \ f4 335 drivers/pinctrl/qcom/pinctrl-msm8x74.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7) \ f4 345 drivers/pinctrl/qcom/pinctrl-msm8x74.c MSM_MUX_##f4, \ f4 32 drivers/pinctrl/qcom/pinctrl-qcs404.c #define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ f4 42 drivers/pinctrl/qcom/pinctrl-qcs404.c msm_mux_##f4, \ f4 30 drivers/pinctrl/qcom/pinctrl-sc7180.c #define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ f4 40 drivers/pinctrl/qcom/pinctrl-sc7180.c msm_mux_##f4, \ f4 36 drivers/pinctrl/qcom/pinctrl-sdm660.c #define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ f4 46 drivers/pinctrl/qcom/pinctrl-sdm660.c msm_mux_##f4, \ f4 25 drivers/pinctrl/qcom/pinctrl-sdm845.c #define PINGROUP(id, base, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10) \ f4 35 drivers/pinctrl/qcom/pinctrl-sdm845.c msm_mux_##f4, \ f4 32 drivers/pinctrl/qcom/pinctrl-sm8150.c #define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ f4 42 drivers/pinctrl/qcom/pinctrl-sm8150.c msm_mux_##f4, \ f4 424 drivers/pinctrl/sh-pfc/pfc-r8a77990.c #define REV8(f0, f1, f2, f3, f4, f5, f6, f7) f0 f4 f2 f6 f1 f5 f3 f7 f4 293 drivers/s390/block/dasd_eckd.h __u8 f4; f4 18 tools/perf/arch/s390/include/dwarf-regs-table.h REG_DWARFNUM_NAME(f4, 18),