f32_cntl          349 drivers/gpu/drm/amd/amdgpu/cik_sdma.c 	u32 f32_cntl, phase_quantum = 0;
f32_cntl          377 drivers/gpu/drm/amd/amdgpu/cik_sdma.c 		f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]);
f32_cntl          379 drivers/gpu/drm/amd/amdgpu/cik_sdma.c 			f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
f32_cntl          388 drivers/gpu/drm/amd/amdgpu/cik_sdma.c 			f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
f32_cntl          392 drivers/gpu/drm/amd/amdgpu/cik_sdma.c 		WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl);
f32_cntl          384 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c 	u32 f32_cntl;
f32_cntl          393 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c 		f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
f32_cntl          395 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c 			f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);
f32_cntl          397 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c 			f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);
f32_cntl          398 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c 		WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);
f32_cntl          558 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 	u32 f32_cntl, phase_quantum = 0;
f32_cntl          586 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 		f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]);
f32_cntl          588 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 			f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
f32_cntl          590 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 			f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
f32_cntl          599 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 			f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
f32_cntl          601 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 			f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
f32_cntl          605 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 		WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl);
f32_cntl          619 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 	u32 f32_cntl;
f32_cntl          628 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 		f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
f32_cntl          630 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 			f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);
f32_cntl          632 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 			f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);
f32_cntl          633 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 		WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);
f32_cntl          889 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 	u32 f32_cntl, phase_quantum = 0;
f32_cntl          917 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 		f32_cntl = RREG32_SDMA(i, mmSDMA0_CNTL);
f32_cntl          918 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 		f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
f32_cntl          925 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 		WREG32_SDMA(i, mmSDMA0_CNTL, f32_cntl);
f32_cntl          940 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 	u32 f32_cntl;
f32_cntl          951 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 		f32_cntl = RREG32_SDMA(i, mmSDMA0_F32_CNTL);
f32_cntl          952 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 		f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
f32_cntl          953 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 		WREG32_SDMA(i, mmSDMA0_F32_CNTL, f32_cntl);
f32_cntl          544 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 	u32 f32_cntl, phase_quantum = 0;
f32_cntl          572 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
f32_cntl          573 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
f32_cntl          583 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
f32_cntl          598 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 	u32 f32_cntl;
f32_cntl          607 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
f32_cntl          608 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
f32_cntl          609 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);