f10               148 arch/ia64/include/uapi/asm/ptrace.h 	struct ia64_fpreg f10;		/* scratch */
f10               123 arch/ia64/kernel/asm-offsets.c 	DEFINE(IA64_PT_REGS_F10_OFFSET, offsetof (struct pt_regs, f10));
f10               204 arch/ia64/kernel/minstate.h 	stf.spill [r2]=f10;			\
f10               126 arch/ia64/kernel/process.c 	       regs->f10.u.bits[1], regs->f10.u.bits[0],
f10               235 arch/ia64/kernel/unaligned.c 	RPT(f10), RPT(f11),
f10                25 arch/mips/include/asm/asmmacro-32.h 	s.d	$f10, THREAD_FPR10(\thread)
f10                49 arch/mips/include/asm/asmmacro-32.h 	l.d	$f10, THREAD_FPR10(\thread)
f10                93 arch/mips/include/asm/asmmacro.h 	sdc1	$f10, THREAD_FPR10(\thread)
f10               152 arch/mips/include/asm/asmmacro.h 	ldc1	$f10, THREAD_FPR10(\thread)
f10                51 arch/mips/include/asm/fpregdef.h #define ft3	$f10
f10                92 arch/mips/include/asm/fpregdef.h #define ft6	$f10
f10               141 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h 		v5, f6, v6, f7, v7, f8, v8, f9, v9, f10, v10)	\
f10               152 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h 				FN(reg, f10), v10)
f10               302 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_10(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10, v10)\
f10               313 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h 				FN(reg, f10), v10)
f10               315 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_14(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\
f10               327 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h 				FN(reg, f10), v10, \
f10               333 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_19(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\
f10               345 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h 				FN(reg, f10), v10, \
f10               356 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h #define REG_UPDATE_20(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\
f10               368 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h 				FN(reg, f10), v10, \
f10               219 drivers/pinctrl/qcom/pinctrl-apq8064.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10) \
f10               235 drivers/pinctrl/qcom/pinctrl-apq8064.c 			APQ_MUX_##f10,			\
f10               226 drivers/pinctrl/qcom/pinctrl-ipq4019.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11, f12, f13, f14) \
f10               242 drivers/pinctrl/qcom/pinctrl-ipq4019.c 			qca_mux_##f10,			\
f10               171 drivers/pinctrl/qcom/pinctrl-ipq8064.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10) \
f10               187 drivers/pinctrl/qcom/pinctrl-ipq8064.c 			IPQ_MUX_##f10,			\
f10               205 drivers/pinctrl/qcom/pinctrl-mdm9615.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \
f10               221 drivers/pinctrl/qcom/pinctrl-mdm9615.c 			MSM_MUX_##f10,			\
f10               344 drivers/pinctrl/qcom/pinctrl-msm8960.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \
f10               360 drivers/pinctrl/qcom/pinctrl-msm8960.c 			MSM_MUX_##f10,			\
f10                20 drivers/pinctrl/qcom/pinctrl-msm8994.c #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11)	\
f10                36 drivers/pinctrl/qcom/pinctrl-msm8994.c 			MSM_MUX_##f10,			\
f10                25 drivers/pinctrl/qcom/pinctrl-sdm845.c #define PINGROUP(id, base, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10)	\
f10                41 drivers/pinctrl/qcom/pinctrl-sdm845.c 			msm_mux_##f10			\
f10                24 tools/perf/arch/s390/include/dwarf-regs-table.h 	REG_DWARFNUM_NAME(f10, 25),