ext_div           692 arch/m68k/include/asm/atarihw.h 	u_char	ext_div;
ext_div           276 arch/mips/netlogic/xlp/nlm_hal.c 	unsigned int pll_divf, pll_divr, dfs_div, ext_div;
ext_div           285 arch/mips/netlogic/xlp/nlm_hal.c 	ext_div  = ((rstval >> 30) & 0x3) + 1;
ext_div           289 arch/mips/netlogic/xlp/nlm_hal.c 	denom = 3 * pll_divr * ext_div * dfs_div;
ext_div           469 drivers/gpu/drm/bridge/tc358767.c 	int ext_div[] = {1, 2, 3, 5, 7};
ext_div           478 drivers/gpu/drm/bridge/tc358767.c 	for (i_pre = 0; i_pre < ARRAY_SIZE(ext_div); i_pre++) {
ext_div           483 drivers/gpu/drm/bridge/tc358767.c 		if (refclk / ext_div[i_pre] < 1000000)
ext_div           485 drivers/gpu/drm/bridge/tc358767.c 		for (i_post = 0; i_post < ARRAY_SIZE(ext_div); i_post++) {
ext_div           490 drivers/gpu/drm/bridge/tc358767.c 				tmp = pixelclock * ext_div[i_pre] *
ext_div           491 drivers/gpu/drm/bridge/tc358767.c 				      ext_div[i_post] * div;
ext_div           499 drivers/gpu/drm/bridge/tc358767.c 				clk = (refclk / ext_div[i_pre] / div) * mul;
ext_div           507 drivers/gpu/drm/bridge/tc358767.c 				clk = clk / ext_div[i_post];
ext_div           530 drivers/gpu/drm/bridge/tc358767.c 		ext_div[best_pre], best_div, best_mul, ext_div[best_post]);
ext_div           533 drivers/gpu/drm/bridge/tc358767.c 	if (refclk / ext_div[best_pre] / best_div * best_mul >= 300000000)
ext_div           547 drivers/gpu/drm/bridge/tc358767.c 	pxl_pllparam |= ext_div[best_pre] << 20; /* External Pre-divider */
ext_div           548 drivers/gpu/drm/bridge/tc358767.c 	pxl_pllparam |= ext_div[best_post] << 16; /* External Post-divider */