exp_resion_start_segment   75 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c 			exp_resion_start_segment, 0);
exp_resion_start_segment   78 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c 			exp_resion_start_segment, 0);
exp_resion_start_segment   81 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c 			exp_resion_start_segment, 0);
exp_resion_start_segment   38 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.h 	type exp_resion_start_segment;\
exp_resion_start_segment  299 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B;
exp_resion_start_segment  300 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	reg->masks.exp_resion_start_segment = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B;
exp_resion_start_segment  326 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B;
exp_resion_start_segment  327 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	reg->masks.exp_resion_start_segment = dpp->tf_mask->CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B;
exp_resion_start_segment  229 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B;
exp_resion_start_segment  230 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	reg->masks.exp_resion_start_segment = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B;
exp_resion_start_segment  232 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c 	reg->shifts.exp_resion_start_segment = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B;
exp_resion_start_segment  233 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c 	reg->masks.exp_resion_start_segment = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B;