exp_region1_lut_offset  118 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c 				exp_region1_lut_offset, curve1->offset,
exp_region1_lut_offset   32 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.h 	type exp_region1_lut_offset; \
exp_region1_lut_offset  284 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET;
exp_region1_lut_offset  285 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET;
exp_region1_lut_offset  311 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET;
exp_region1_lut_offset  312 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET;
exp_region1_lut_offset  214 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET;
exp_region1_lut_offset  215 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET;
exp_region1_lut_offset  218 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c 	reg->shifts.exp_region1_lut_offset = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET;
exp_region1_lut_offset  219 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c 	reg->masks.exp_region1_lut_offset = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET;