exp_region0_lut_offset  116 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c 				exp_region0_lut_offset, curve0->offset,
exp_region0_lut_offset   30 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.h 	type exp_region0_lut_offset; \
exp_region0_lut_offset  280 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET;
exp_region0_lut_offset  281 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET;
exp_region0_lut_offset  307 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET;
exp_region0_lut_offset  308 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET;
exp_region0_lut_offset  210 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET;
exp_region0_lut_offset  211 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c 	reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET;
exp_region0_lut_offset  214 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c 	reg->shifts.exp_region0_lut_offset = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET;
exp_region0_lut_offset  215 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c 	reg->masks.exp_region0_lut_offset = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET;