Fcw1_int           77 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h 	uint16_t    Fcw1_int;
Fcw1_int           75 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h 	uint16_t    Fcw1_int;
Fcw1_int          865 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int;
Fcw1_int          896 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		sclk_setting->Fcw1_int = (uint16_t)((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
Fcw1_int          971 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_int);
Fcw1_int         1243 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_int);
Fcw1_int          740 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int;
Fcw1_int          775 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		sclk_setting->Fcw1_int = (uint16_t)
Fcw1_int          855 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_int);
Fcw1_int         1155 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_int);