evts 606 arch/alpha/kernel/perf_event.c struct perf_event *evts[MAX_HWEVENTS]; evts 652 arch/alpha/kernel/perf_event.c evts, evtypes, idx_rubbish_bin); evts 657 arch/alpha/kernel/perf_event.c evts[n] = event; evts 659 arch/alpha/kernel/perf_event.c if (alpha_check_constraints(evts, evtypes, n + 1)) evts 1242 arch/sparc/kernel/perf_event.c static int sparc_check_constraints(struct perf_event **evts, evts 1261 arch/sparc/kernel/perf_event.c evts[i]->hw.idx = i; evts 1308 arch/sparc/kernel/perf_event.c evts[0]->hw.idx = idx0; evts 1310 arch/sparc/kernel/perf_event.c evts[1]->hw.idx = idx0 ^ 1; evts 1314 arch/sparc/kernel/perf_event.c static int check_excludes(struct perf_event **evts, int n_prev, int n_new) evts 1329 arch/sparc/kernel/perf_event.c event = evts[i]; evts 1346 arch/sparc/kernel/perf_event.c struct perf_event *evts[], unsigned long *events, evts 1355 arch/sparc/kernel/perf_event.c evts[n] = group; evts 1364 arch/sparc/kernel/perf_event.c evts[n] = event; evts 1418 arch/sparc/kernel/perf_event.c struct perf_event *evts[MAX_HWEVENTS]; evts 1477 arch/sparc/kernel/perf_event.c evts, events, current_idx_dmy); evts 1482 arch/sparc/kernel/perf_event.c evts[n] = event; evts 1484 arch/sparc/kernel/perf_event.c if (check_excludes(evts, n, 1)) evts 1487 arch/sparc/kernel/perf_event.c if (sparc_check_constraints(evts, events, n + 1)) evts 441 drivers/firewire/ohci.c static const char *evts[] = { evts 480 drivers/firewire/ohci.c if (unlikely(evt >= ARRAY_SIZE(evts))) evts 505 drivers/firewire/ohci.c dir, evts[evt], tcodes[tcode]); evts 509 drivers/firewire/ohci.c dir, evts[evt], header[1], header[2]); evts 515 drivers/firewire/ohci.c header[1] >> 16, header[0] >> 16, evts[evt], evts 522 drivers/firewire/ohci.c header[1] >> 16, header[0] >> 16, evts[evt], evts 1660 drivers/firewire/ohci.c name, evts[ctl & 0x1f]); evts 16 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c u64 evts = 0ULL; evts 20 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c evts |= KOMEDA_EVENT_IBSY; evts 22 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c evts |= KOMEDA_EVENT_EOW; evts 30 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c evts |= KOMEDA_ERR_AXIE; evts 34 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c evts |= KOMEDA_ERR_ACE0; evts 38 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c evts |= KOMEDA_ERR_ACE1; evts 42 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c evts |= KOMEDA_ERR_ACE2; evts 46 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c evts |= KOMEDA_ERR_ACE3; evts 56 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c evts |= KOMEDA_ERR_TCF; evts 60 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c evts |= KOMEDA_ERR_TTNG; evts 64 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c evts |= KOMEDA_ERR_TITR; evts 68 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c evts |= KOMEDA_ERR_TEMR; evts 72 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c evts |= KOMEDA_ERR_TTF; evts 79 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c return evts; evts 86 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c u64 evts = 0ULL; evts 90 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c evts |= KOMEDA_EVENT_OVR; evts 95 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c evts |= KOMEDA_ERR_CPE; evts 97 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c evts |= KOMEDA_ERR_ZME; evts 99 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c evts |= KOMEDA_ERR_CFGE; evts 106 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c return evts; evts 113 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c u64 evts = 0ULL; evts 117 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c evts |= KOMEDA_EVENT_VSYNC; evts 119 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c evts |= KOMEDA_EVENT_URUN; evts 127 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c evts |= KOMEDA_ERR_DRIFTTO; evts 131 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c evts |= KOMEDA_ERR_FRAMETO; evts 135 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c evts |= KOMEDA_ERR_TETO; evts 139 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c evts |= KOMEDA_ERR_CSCE; evts 147 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c return evts; evts 152 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c u32 evts = 0ULL; evts 155 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c evts |= get_lpu_event(d71_pipeline); evts 158 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c evts |= get_cu_event(d71_pipeline); evts 161 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c evts |= get_dou_event(d71_pipeline); evts 163 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c return evts; evts 167 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c d71_irq_handler(struct komeda_dev *mdev, struct komeda_events *evts) evts 177 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c evts->pipes[0] |= KOMEDA_EVENT_FLIP; evts 179 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c evts->pipes[1] |= KOMEDA_EVENT_FLIP; evts 183 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c evts->global |= KOMEDA_ERR_MERR; evts 193 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c evts->pipes[0] |= get_pipeline_event(d71->pipes[0], gcu_status); evts 196 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c evts->pipes[1] |= get_pipeline_event(d71->pipes[1], gcu_status); evts 171 drivers/gpu/drm/arm/display/komeda/komeda_crtc.c struct komeda_events *evts) evts 174 drivers/gpu/drm/arm/display/komeda/komeda_crtc.c u32 events = evts->pipes[kcrtc->master->id]; evts 43 drivers/gpu/drm/arm/display/komeda/komeda_kms.c struct komeda_events evts; evts 48 drivers/gpu/drm/arm/display/komeda/komeda_kms.c memset(&evts, 0, sizeof(evts)); evts 49 drivers/gpu/drm/arm/display/komeda/komeda_kms.c status = mdev->funcs->irq_handler(mdev, &evts); evts 53 drivers/gpu/drm/arm/display/komeda/komeda_kms.c komeda_crtc_handle_event(&kms->crtcs[i], &evts); evts 182 drivers/gpu/drm/arm/display/komeda/komeda_kms.h struct komeda_events *evts); evts 71 drivers/gpu/drm/gma500/opregion.c u32 evts; /* ASL supported events */ evts 91 drivers/gpu/drm/i915/display/intel_opregion.c u32 evts; /* ASL supported events */ evts 791 drivers/i3c/master.c u8 addr, bool enable, u8 evts) evts 802 drivers/i3c/master.c events->events = evts; evts 829 drivers/i3c/master.c u8 evts) evts 831 drivers/i3c/master.c return i3c_master_enec_disec_locked(master, addr, false, evts); evts 850 drivers/i3c/master.c u8 evts) evts 852 drivers/i3c/master.c return i3c_master_enec_disec_locked(master, addr, true, evts); evts 45 drivers/iommu/virtio-iommu.c void *evts; evts 988 drivers/iommu/virtio-iommu.c struct viommu_event *evts; evts 992 drivers/iommu/virtio-iommu.c viommu->evts = evts = devm_kmalloc_array(viommu->dev, nr_evts, evts 993 drivers/iommu/virtio-iommu.c sizeof(*evts), GFP_KERNEL); evts 994 drivers/iommu/virtio-iommu.c if (!evts) evts 998 drivers/iommu/virtio-iommu.c sg_init_one(sg, &evts[i], sizeof(*evts)); evts 999 drivers/iommu/virtio-iommu.c ret = virtqueue_add_inbuf(vq, sg, 1, &evts[i], GFP_KERNEL); evts 209 drivers/rtc/rtc-stm32.c const struct stm32_rtc_events *evts = &rtc->data->events; evts 217 drivers/rtc/rtc-stm32.c if ((status & evts->alra) && evts 226 drivers/rtc/rtc-stm32.c stm32_rtc_clear_event_flags(rtc, evts->alra); evts 340 drivers/rtc/rtc-stm32.c const struct stm32_rtc_events *evts = &rtc->data->events; evts 399 drivers/rtc/rtc-stm32.c alrm->pending = (status & evts->alra) ? 1 : 0; evts 408 drivers/rtc/rtc-stm32.c const struct stm32_rtc_events *evts = &rtc->data->events; evts 423 drivers/rtc/rtc-stm32.c stm32_rtc_clear_event_flags(rtc, evts->alra); evts 17 drivers/virtio/virtio_input.c struct virtio_input_event evts[64]; evts 193 drivers/virtio/virtio_input.c if (size > ARRAY_SIZE(vi->evts)) evts 194 drivers/virtio/virtio_input.c size = ARRAY_SIZE(vi->evts); evts 196 drivers/virtio/virtio_input.c virtinput_queue_evtbuf(vi, &vi->evts[i]); evts 525 include/linux/i3c/master.h u8 evts); evts 527 include/linux/i3c/master.h u8 evts);