eventsel 277 arch/x86/events/amd/core.c static inline int amd_pmu_addr_offset(int index, bool eventsel) eventsel 284 arch/x86/events/amd/core.c if (eventsel) eventsel 297 arch/x86/events/amd/core.c if (eventsel) eventsel 910 arch/x86/events/amd/core.c .eventsel = MSR_K7_EVNTSEL0, eventsel 950 arch/x86/events/amd/core.c x86_pmu.eventsel = MSR_F15H_PERF_CTL; eventsel 3885 arch/x86/events/intel/core.c .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, eventsel 3931 arch/x86/events/intel/core.c .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, eventsel 299 arch/x86/events/intel/knc.c .eventsel = MSR_KNC_EVNTSEL0, eventsel 1308 arch/x86/events/intel/p4.c .eventsel = MSR_P4_BPU_CCCR0, eventsel 210 arch/x86/events/intel/p6.c .eventsel = MSR_P6_EVNTSEL0, eventsel 582 arch/x86/events/perf_event.h unsigned eventsel; eventsel 584 arch/x86/events/perf_event.h int (*addr_offset)(int index, bool eventsel); eventsel 802 arch/x86/events/perf_event.h return x86_pmu.eventsel + (x86_pmu.addr_offset ? eventsel 454 arch/x86/include/asm/kvm_host.h u64 eventsel; eventsel 143 arch/x86/kvm/pmu.c void reprogram_gp_counter(struct kvm_pmc *pmc, u64 eventsel) eventsel 152 arch/x86/kvm/pmu.c if (eventsel & ARCH_PERFMON_EVENTSEL_PIN_CONTROL) eventsel 155 arch/x86/kvm/pmu.c pmc->eventsel = eventsel; eventsel 159 arch/x86/kvm/pmu.c if (!(eventsel & ARCH_PERFMON_EVENTSEL_ENABLE) || !pmc_is_enabled(pmc)) eventsel 166 arch/x86/kvm/pmu.c (eventsel & AMD64_RAW_EVENT_MASK_NB)) eventsel 178 arch/x86/kvm/pmu.c event_select = eventsel & ARCH_PERFMON_EVENTSEL_EVENT; eventsel 179 arch/x86/kvm/pmu.c unit_mask = (eventsel & ARCH_PERFMON_EVENTSEL_UMASK) >> 8; eventsel 181 arch/x86/kvm/pmu.c if (!(eventsel & (ARCH_PERFMON_EVENTSEL_EDGE | eventsel 194 arch/x86/kvm/pmu.c config = eventsel & X86_RAW_EVENT_MASK; eventsel 197 arch/x86/kvm/pmu.c !(eventsel & ARCH_PERFMON_EVENTSEL_USR), eventsel 198 arch/x86/kvm/pmu.c !(eventsel & ARCH_PERFMON_EVENTSEL_OS), eventsel 199 arch/x86/kvm/pmu.c eventsel & ARCH_PERFMON_EVENTSEL_INT, eventsel 200 arch/x86/kvm/pmu.c (eventsel & HSW_IN_TX), eventsel 201 arch/x86/kvm/pmu.c (eventsel & HSW_IN_TX_CHECKPOINTED)); eventsel 243 arch/x86/kvm/pmu.c reprogram_gp_counter(pmc, pmc->eventsel); eventsel 19 arch/x86/kvm/pmu.h u8 eventsel; eventsel 116 arch/x86/kvm/pmu.h void reprogram_gp_counter(struct kvm_pmc *pmc, u64 eventsel); eventsel 136 arch/x86/kvm/pmu_amd.c if (amd_event_mapping[i].eventsel == event_select eventsel 225 arch/x86/kvm/pmu_amd.c *data = pmc->eventsel; eventsel 248 arch/x86/kvm/pmu_amd.c if (data == pmc->eventsel) eventsel 300 arch/x86/kvm/pmu_amd.c pmc->counter = pmc->eventsel = 0; eventsel 74 arch/x86/kvm/vmx/pmu_intel.c if (intel_arch_events[i].eventsel == event_select eventsel 201 arch/x86/kvm/vmx/pmu_intel.c *data = pmc->eventsel; eventsel 258 arch/x86/kvm/vmx/pmu_intel.c if (data == pmc->eventsel) eventsel 358 arch/x86/kvm/vmx/pmu_intel.c pmc->counter = pmc->eventsel = 0; eventsel 368 drivers/gpu/drm/amd/amdgpu/df_v3_6.c uint32_t eventsel, instance, unitmask; eventsel 379 drivers/gpu/drm/amd/amdgpu/df_v3_6.c eventsel = DF_V3_6_GET_EVENT(config) & 0x3f; eventsel 387 drivers/gpu/drm/amd/amdgpu/df_v3_6.c *lo_val = (unitmask << 8) | (instance_10 << 6) | eventsel | (1 << 22); eventsel 86 virt/kvm/arm/pmu.c u64 eventsel, reg; eventsel 94 virt/kvm/arm/pmu.c eventsel = __vcpu_sys_reg(vcpu, reg) & ARMV8_PMU_EVTYPE_EVENT; eventsel 96 virt/kvm/arm/pmu.c return eventsel == ARMV8_PMUV3_PERFCTR_CHAIN; eventsel 570 virt/kvm/arm/pmu.c u64 eventsel, counter, reg, data; eventsel 584 virt/kvm/arm/pmu.c eventsel = data & ARMV8_PMU_EVTYPE_EVENT; eventsel 587 virt/kvm/arm/pmu.c if (eventsel == ARMV8_PMUV3_PERFCTR_SW_INCR && eventsel 601 virt/kvm/arm/pmu.c ARMV8_PMUV3_PERFCTR_CPU_CYCLES : eventsel;