event_base 351 arch/alpha/kernel/perf_event.c evtype[n] = group->hw.event_base; event_base 359 arch/alpha/kernel/perf_event.c evtype[n] = pe->hw.event_base; event_base 459 arch/alpha/kernel/perf_event.c cpuc->evtype[n0] = event->hw.event_base; event_base 642 arch/alpha/kernel/perf_event.c hwc->event_base = ev; event_base 656 arch/alpha/kernel/perf_event.c evtypes[n] = hwc->event_base; event_base 294 arch/mips/kernel/perf_event_mipsxx.c unsigned long cntr_mask = (hwc->event_base >> 8) & 0xffff; event_base 319 arch/mips/kernel/perf_event_mipsxx.c unsigned int range = evt->event_base >> 24; event_base 323 arch/mips/kernel/perf_event_mipsxx.c cpuc->saved_ctrl[idx] = M_PERFCTL_EVENT(evt->event_base & 0xff) | event_base 1314 arch/mips/kernel/perf_event_mipsxx.c hwc->event_base = mipspmu_perf_event_encode(pev); event_base 819 arch/nds32/kernel/perf_event_cpu.c hwc->event_base = 0; event_base 1447 arch/powerpc/perf/core-book3s.c flags[n] = group->hw.event_base; event_base 1456 arch/powerpc/perf/core-book3s.c flags[n] = event->hw.event_base; event_base 1489 arch/powerpc/perf/core-book3s.c cpuhw->flags[n0] = event->hw.event_base; event_base 1970 arch/powerpc/perf/core-book3s.c event->hw.event_base = cflags[n]; event_base 538 arch/powerpc/perf/imc-pmu.c event->hw.event_base = (u64)pcni->vbase + l_config; event_base 822 arch/powerpc/perf/imc-pmu.c event->hw.event_base = (u64)pcmi->vbase + (config & IMC_EVENT_OFFSET_MASK); event_base 940 arch/powerpc/perf/imc-pmu.c return (u64 *)event->hw.event_base; event_base 70 arch/s390/include/asm/perf_event.h #define SAMPL_RATE(hwc) ((hwc)->event_base) event_base 1356 arch/sparc/kernel/perf_event.c events[n] = group->hw.event_base; event_base 1365 arch/sparc/kernel/perf_event.c events[n] = event->hw.event_base; event_base 1385 arch/sparc/kernel/perf_event.c cpuc->events[n0] = event->hw.event_base; event_base 1455 arch/sparc/kernel/perf_event.c hwc->event_base = perf_event_encode(pmap); event_base 1461 arch/sparc/kernel/perf_event.c hwc->event_base = attr->config; event_base 1481 arch/sparc/kernel/perf_event.c events[n] = hwc->event_base; event_base 106 arch/x86/events/amd/uncore.c wrmsrl(hwc->event_base, (u64)local64_read(&hwc->prev_count)); event_base 157 arch/x86/events/amd/uncore.c hwc->event_base = uncore->msr_base + 1 + (2 * hwc->idx); event_base 1069 arch/x86/events/core.c hwc->event_base = 0; event_base 1072 arch/x86/events/core.c hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - INTEL_PMC_IDX_FIXED); event_base 1076 arch/x86/events/core.c hwc->event_base = x86_pmu_event_addr(hwc->idx); event_base 1237 arch/x86/events/core.c wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask); event_base 1245 arch/x86/events/core.c wrmsrl(hwc->event_base, event_base 2286 arch/x86/events/intel/core.c wrmsrl(event->hw.event_base, 0); event_base 325 arch/x86/events/intel/cstate.c event->hw.event_base = core_msr[cfg].msr; event_base 334 arch/x86/events/intel/cstate.c event->hw.event_base = pkg_msr[cfg].msr; event_base 354 arch/x86/events/intel/cstate.c rdmsrl(event->hw.event_base, val); event_base 873 arch/x86/events/intel/p4.c rdmsrl(hwc->event_base, v); event_base 157 arch/x86/events/intel/rapl.c rdmsrl(event->hw.event_base, raw); event_base 185 arch/x86/events/intel/rapl.c rdmsrl(event->hw.event_base, new_raw_count); event_base 369 arch/x86/events/intel/rapl.c event->hw.event_base = rapl_msrs[bit].msr; event_base 118 arch/x86/events/intel/uncore.c rdmsrl(event->hw.event_base, count); event_base 135 arch/x86/events/intel/uncore.c return readq(box->io_addr + event->hw.event_base); event_base 224 arch/x86/events/intel/uncore.c hwc->event_base = uncore_fixed_ctr(box); event_base 230 arch/x86/events/intel/uncore.c hwc->event_base = uncore_perf_ctr(box, hwc->idx); event_base 758 arch/x86/events/intel/uncore.c event->hw.event_base = uncore_freerunning_counter(box, event); event_base 513 arch/x86/events/intel/uncore_snb.c event->hw.event_base = base; event_base 509 arch/x86/events/intel/uncore_snbep.c pci_read_config_dword(pdev, hwc->event_base, (u32 *)&count); event_base 510 arch/x86/events/intel/uncore_snbep.c pci_read_config_dword(pdev, hwc->event_base + 4, (u32 *)&count + 1); event_base 209 arch/x86/events/msr.c event->hw.event_base = msr[cfg].msr; event_base 219 arch/x86/events/msr.c if (event->hw.event_base) event_base 220 arch/x86/events/msr.c rdmsrl(event->hw.event_base, now); event_base 241 arch/x86/events/msr.c if (unlikely(event->hw.event_base == MSR_SMI_COUNT)) { event_base 244 arch/x86/events/msr.c } else if (unlikely(event->hw.event_base == MSR_IA32_THERM_STATUS)) { event_base 34 drivers/clocksource/timer-qcom.c static void __iomem *event_base; event_base 42 drivers/clocksource/timer-qcom.c u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE); event_base 44 drivers/clocksource/timer-qcom.c writel_relaxed(ctrl, event_base + TIMER_ENABLE); event_base 53 drivers/clocksource/timer-qcom.c u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE); event_base 56 drivers/clocksource/timer-qcom.c writel_relaxed(ctrl, event_base + TIMER_ENABLE); event_base 58 drivers/clocksource/timer-qcom.c writel_relaxed(ctrl, event_base + TIMER_CLEAR); event_base 59 drivers/clocksource/timer-qcom.c writel_relaxed(cycles, event_base + TIMER_MATCH_VAL); event_base 65 drivers/clocksource/timer-qcom.c writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE); event_base 73 drivers/clocksource/timer-qcom.c ctrl = readl_relaxed(event_base + TIMER_ENABLE); event_base 75 drivers/clocksource/timer-qcom.c writel_relaxed(ctrl, event_base + TIMER_ENABLE); event_base 240 drivers/clocksource/timer-qcom.c event_base = base + 0x4; event_base 1302 drivers/perf/arm-cci.c hwc->event_base = 0; event_base 907 drivers/perf/arm-ccn.c dt_cfg = hw->event_base; event_base 961 drivers/perf/arm-ccn.c hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__WATCHPOINT(wp); event_base 1004 drivers/perf/arm-ccn.c hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__XP_PMU_EVENT(hw->config_base); event_base 1027 drivers/perf/arm-ccn.c hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__DEVICE_PMU_EVENT(port, event_base 385 drivers/perf/arm_pmu.c hwc->event_base = 0; event_base 252 drivers/perf/thunderx2_pmu.c hwc->event_base = (unsigned long)tx2_pmu->base event_base 264 drivers/perf/thunderx2_pmu.c hwc->event_base = (unsigned long)tx2_pmu->base event_base 277 drivers/perf/thunderx2_pmu.c reg_writel(0, hwc->event_base); event_base 300 drivers/perf/thunderx2_pmu.c reg_writel(0, hwc->event_base); event_base 327 drivers/perf/thunderx2_pmu.c new = reg_readl(hwc->event_base); event_base 128 include/linux/perf_event.h unsigned long event_base;