eu_mask            40 drivers/gpu/drm/i915/gt/intel_sseu.h 	u8 eu_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICES];
eu_mask          3766 drivers/gpu/drm/i915/i915_debugfs.c 	u32 s_reg[SS_MAX], eu_reg[2 * SS_MAX], eu_mask[2];
eu_mask          3782 drivers/gpu/drm/i915/i915_debugfs.c 	eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
eu_mask          3786 drivers/gpu/drm/i915/i915_debugfs.c 	eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
eu_mask          3807 drivers/gpu/drm/i915/i915_debugfs.c 					       eu_mask[ss % 2]);
eu_mask          3822 drivers/gpu/drm/i915/i915_debugfs.c 	u32 s_reg[SS_MAX], eu_reg[2 * SS_MAX], eu_mask[2];
eu_mask          3831 drivers/gpu/drm/i915/i915_debugfs.c 	eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
eu_mask          3835 drivers/gpu/drm/i915/i915_debugfs.c 	eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
eu_mask          3863 drivers/gpu/drm/i915/i915_debugfs.c 					       eu_mask[ss%2]);
eu_mask            92 drivers/gpu/drm/i915/i915_query.c 			   sseu->eu_mask, eu_length))
eu_mask           131 drivers/gpu/drm/i915/intel_device_info.c 	u16 eu_mask = 0;
eu_mask           134 drivers/gpu/drm/i915/intel_device_info.c 		eu_mask |= ((u16)sseu->eu_mask[offset + i]) <<
eu_mask           138 drivers/gpu/drm/i915/intel_device_info.c 	return eu_mask;
eu_mask           142 drivers/gpu/drm/i915/intel_device_info.c 			 u16 eu_mask)
eu_mask           147 drivers/gpu/drm/i915/intel_device_info.c 		sseu->eu_mask[offset + i] =
eu_mask           148 drivers/gpu/drm/i915/intel_device_info.c 			(eu_mask >> (BITS_PER_BYTE * i)) & 0xff;
eu_mask           180 drivers/gpu/drm/i915/intel_device_info.c 	for (i = 0; i < ARRAY_SIZE(sseu->eu_mask); i++)
eu_mask           181 drivers/gpu/drm/i915/intel_device_info.c 		total += hweight8(sseu->eu_mask[i]);
eu_mask           236 drivers/gpu/drm/i915/intel_device_info.c 	const int eu_mask = 0xff;
eu_mask           260 drivers/gpu/drm/i915/intel_device_info.c 		sseu_set_eus(sseu, 0, ss, (eu_en >> (8 * ss)) & eu_mask);
eu_mask           262 drivers/gpu/drm/i915/intel_device_info.c 	sseu_set_eus(sseu, 1, 0, (eu_en >> 24) & eu_mask);
eu_mask           264 drivers/gpu/drm/i915/intel_device_info.c 	sseu_set_eus(sseu, 1, 1, eu_en & eu_mask);
eu_mask           266 drivers/gpu/drm/i915/intel_device_info.c 	sseu_set_eus(sseu, 2, 0, (eu_en >> 8) & eu_mask);
eu_mask           267 drivers/gpu/drm/i915/intel_device_info.c 	sseu_set_eus(sseu, 2, 1, (eu_en >> 16) & eu_mask);
eu_mask           269 drivers/gpu/drm/i915/intel_device_info.c 	sseu_set_eus(sseu, 3, 0, (eu_en >> 24) & eu_mask);
eu_mask           271 drivers/gpu/drm/i915/intel_device_info.c 	sseu_set_eus(sseu, 3, 1, eu_en & eu_mask);
eu_mask           273 drivers/gpu/drm/i915/intel_device_info.c 	sseu_set_eus(sseu, 4, 0, (eu_en >> 8) & eu_mask);
eu_mask           274 drivers/gpu/drm/i915/intel_device_info.c 	sseu_set_eus(sseu, 4, 1, (eu_en >> 16) & eu_mask);
eu_mask           276 drivers/gpu/drm/i915/intel_device_info.c 	sseu_set_eus(sseu, 5, 0, (eu_en >> 24) & eu_mask);
eu_mask           278 drivers/gpu/drm/i915/intel_device_info.c 	sseu_set_eus(sseu, 5, 1, eu_en & eu_mask);
eu_mask           369 drivers/gpu/drm/i915/intel_device_info.c 	const u8 eu_mask = 0xff;
eu_mask           407 drivers/gpu/drm/i915/intel_device_info.c 			eu_disabled_mask = (eu_disable >> (ss * 8)) & eu_mask;