FP6               294 arch/powerpc/xmon/spu-insns.h APUOP(M_FA,		RR,	0x2c4,	"fa",		_A3(A_T,A_A,A_B),		00112,	FP6)	/* FAdd          RT<-RA+RB */
FP6               295 arch/powerpc/xmon/spu-insns.h APUOP(M_FM,		RR,	0x2c6,	"fm",		_A3(A_T,A_A,A_B),		00112,	FP6)	/* FMul          RT<-RA*RB */
FP6               296 arch/powerpc/xmon/spu-insns.h APUOP(M_FS,		RR,	0x2c5,	"fs",		_A3(A_T,A_A,A_B),		00112,	FP6)	/* FSub          RT<-RA-RB */
FP6               318 arch/powerpc/xmon/spu-insns.h APUOP(M_FMA,		RRR,	0x700,	"fma",		_A4(A_C,A_A,A_B,A_T),	02111,	FP6)	/* FMAdd         RC<-RT+RA*RB */
FP6               319 arch/powerpc/xmon/spu-insns.h APUOP(M_FMS,		RRR,	0x780,	"fms",		_A4(A_C,A_A,A_B,A_T),	02111,	FP6)	/* FMSub         RC<-RA*RB-RT */
FP6               320 arch/powerpc/xmon/spu-insns.h APUOP(M_FNMS,		RRR,	0x680,	"fnms",		_A4(A_C,A_A,A_B,A_T),	02111,	FP6)	/* FNMSub        RC<-RT-RA*RB */
FP6                44 tools/perf/arch/s390/util/unwind-libdw.c 	dwarf_regs[19] = REG(FP6);